Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced immediate availability of the 65-nanometer Common Power Format (CPF) enabled reference flow targeting the Common Platform(TM) technology. This reference flow is the next step in the ongoing collaboration between Cadence(R) and the Common Platform coalition comprised of IBM, Chartered Semiconductor Manufacturing and Samsung.
Cadence worked closely with the Common Platform technology partners to develop this 65-nanometer flow. It is based on the Cadence digital IC design platform including Encounter(R) Timing System and CPF to accelerate time to market for low-power system-on-chip (SoC) designs.
“Cadence has worked actively with the Common Platform technology manufacturers to develop this reference flow that enhances our 65-nanometer design enablement portfolio,” said Steve Longoria, vice president of Semiconductor Technology Platform for IBM Global Engineering Solutions. “The Common Platform technology companies worked with Cadence engineers to deliver this 65-nanometer reference flow using the ARM-Metro libraries and the Cadence Encounter platform. The result is a solution that will bring advanced low-power technology to designers challenged with issues such as battery life and energy conservation in mobile devices and other consumer applications.”
This RTL-to-GDSII reference flow is based on the Cadence Encounter digital IC design platform and enables higher productivity and improved quality of silicon (QoS). The flow addresses critical low-power design challenges, from chip prototyping through power, timing and area optimization and is targeted for wireless, wireline and consumer applications.
“Collaborating with Cadence is an important part of Samsung’s strategy to enable the design chain to bring advanced low-power design methodologies to our foundry customers,” said Dr. Ben Suh, vice president, ASIC & Foundry Business Development, System LSI Division at Samsung Electronics. “This low-power reference flow, targeted to the 65-nanometer LP process, accelerates the time to volume for foundry customers bringing new designs to Samsung for manufacturing.”
“We recognize that customers today want solutions to help address power concerns and they want to ensure they have a choice in their solutions. In this case, we are working with Cadence and our Common Platform partners to deliver solutions that accelerate designs to silicon while offering customers the flexibility in sourcing options through the collaborative strategy of the Common Platform,” said Kevin Meyer, vice president of worldwide marketing and platform alliances at Chartered. “The delivery of this 65-nanometer reference flow makes available an innovative low-power design solution for Chartered customers.”
The flow incorporates several innovative technologies in the Encounter platform as well as the Cadence Logic Design Team Solution, including Cadence Encounter RTL Compiler with global synthesis technology, the Cadence SoC Encounter? RTL-to-GDSII system, Cadence Encounter Test and Cadence Encounter Conformal(R) Low-Power. Other Cadence components include VoltageStorm(R) power analysis, and Encounter Timing System using the effective current source model (ECSM) to enable designers to reduce time to volume for low-power consumer applications. ARM(R) Metro(TM) low-power products, part of its family of Artisan(R) physical IP, are used for the flow development.
“ARM and Cadence continue our long-term relationship with ARM Metro low-power IP being an integral component of the reference flow targeting the Common Platform technology,” said Tom Lantzsch, vice president of marketing, Physical IP, ARM. “Working with the Common Platform technology partners and Cadence provides manufacturing flexibility along with advanced design solutions to accelerate time to market for our mutual customers.”
“Our design chain collaboration with leaders of the Common Platform is what makes new technology like the CPF-based Cadence Low Power Solution a reality,” said Jan Willis, senior vice president, Industry Alliances, at Cadence. “This 65-nanometer low-power reference flow provides an integrated methodology for customers to deliver low-power products in volume using CPF with the Common Platform technology.”
This 65-nanometer low-power, yield-aware design reference flow is available immediately by sending an email request to common_platform_65LP@cadence.com. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.
On Wednesday, June 13, 2007, at 4 pm (PDT), Cadence, Chartered, IBM and Samsung will hold a free Webinar on advanced low-power design techniques used in this reference flow.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Encounter, Conformal and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks, of Cadence Design Systems, Inc. in the U.S. and other countries.