Apache Design Solutions, the technology leader in power sign-off and complete silicon integrity platform solutions for system-on-chip (SoC) designs, announced RedHawk-ALP, a physical power integrity solution for advanced low power and leakage control designs. RedHawk-ALP targets power savings and leakage control techniques used in 65/45nm designs including:
- VTCMOS (Variable Threshold CMOS) circuits with substrate back-biasing
- Power-gated memories and custom macros
- On-chip LDO (Low Drop-Out) voltage regulators
Apache lead the market in delivering the first dynamic solution, RedHawk-LP, for MTCMOS (Multiple Threshold CMOS) ramp-up and rush current analyses, power switch optimizations, and full-chip mixed-mode verification. As designs move towards 45nm, designers are faced with new challenges which require even more aggressive techniques to reduce leakage. With RedHawk-ALP, Apache extends its low power leadership position to be the first in the market to provide a comprehensive solution that addresses these advanced techniques.
VTCMOS is a new circuit technique for reducing the leakage current by dynamically altering the substrate voltage. However, varying of the substrate voltage introduces noise on the supply source and increases variability in circuit behavior. Apache’s RedHawk-ALP accurately extracts bias networks and analyzes full-chip dynamic power integrity including instance-based Vsub(t) and Isub(t) for design tradeoff analysis.
MTCMOS, or power-gating, has been widely used for reducing leakage by controlling the on/off switching of logic blocks or cells in 90/65nm designs. As designs move towards 45nm, designers must add power switches to memories and custom IP to further reduce leakage. RedHawk-ALP expands modeling capabilities and simulation capacity of the existing cell- / block-level MTCMOS support to handle large GDS-based custom macros.
On-chip LDOs are often used to deliver the desired voltages to different parts of the chip (voltage islands) without introducing extra power pins. Since LDO is an analog circuit with a continuous output voltage waveform, designers traditionally had to use Spice to simulate its behavior. At the full-chip level, LDO was typically modeled by an ideal voltage source, which hides the potential power noise generated by the LDO circuit. Apache’s RedHawk-ALP accurately models LDO circuit and provides the true transient behavior for full-chip power noise analysis.
“Apache continues to lead the market in addressing the critical design needs as we move toward 65 and 45nm processes,” said Dian Yang, vice president of product management at Apache. “Our new product enables IC designers to better understand the behavior of advanced low power techniques and to allow designers to make effective leakage versus performance tradeoff decisions. RedHawk-ALP is Apache’s continued commitment to expand our solutions for critical silicon integrity signoff.”
Pricing and Availability
RedHawk-ALP is available as beta now and will be available for production use in Q3, 2007. An annual licensing start at $330,000 US list and is upgradeable from existing RedHawk-LP license.
RedHawk is a full-chip Vectorless Dynamic(TM) physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as effects of on-chip inductance, package RLC, and decoupling capacitance. RedHawk delivers transistor-level accuracy with cell-based capacity, performance, and ease-of-use.
With RedHawk, designers can identify dynamic “hot spots,” examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. RedHawk enables designers to reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, MTCMOS (power-gating), multiple voltage domains, and multiple threshold transistors.
About Apache Design Solutions
Apache delivers the leading power sign-off solution adopted by 70% of top semiconductor companies and a complete platform solution for silicon integrity of low-power, high-performance system-on-a-chip (SoC) designs. Apache’s innovative platform considers all sources of noise that impacts the design–such as power, signal, package / system IO, substrate, and temperature–Apache’s silicon integrity platform enables designers of leading networking, wireless, communication, consumer, and semiconductor companies to detect, fix, and prevent design weaknesses that can result in reduced yield or failed silicon. Apache’s vendor-neutral solutions enable designers to adopt any industry-standard physical design flow and are certified by TSMC’s 5.0, 6.0, and 7.0 Reference Flow (NYSE: TSM). Apache has direct sales and support offices worldwide with over 40 customers, including 8 of the top 10 semiconductor companies.
Apache Design Solutions, NSPICE, RedHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc.