Calypto(TM) Design Systems Inc., the leader in sequential analysis technology, will participate in two workshops during Design Automation and Test in Europe (DATE) 07 next week at the Nice Acropolis in Nice, France.
The first, “Common Power Format Workshop on Standards for Low-Power Design Intent,” is sponsored by Silicon Integration Initiative (Si2) and will be held Wednesday, April 18, from 10 a.m. to noon in Room Maia on the Rhodes Level. Calypto’s presentation by Product Marketing Director Mitch Dale follows an announcement this week that Calypto added support for Si2′s Common Power Format 1.0 (CPF) to its PowerPro(TM) CG product. PowerPro CG has reduced power in customer designs by up to 60% with no impact to functionality, area or performance.
The second workshop, “System Design: From Algorithm to RTL,” will feature product demonstrations from Calypto, The MathWorks, VaST Systems and Forte Design Systems working in concert to create a complete design flow. Calypto will show how its SLEC(TM) (Sequential Logic Equivalence Checking) product verifies register transfer level (RTL) implementations by leveraging system models. The workshop will be held April 18 from 3:30-5:30 p.m. in Room Maia on the Rhodes Level.
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email: email@example.com.
Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc.