Sequence Design announced DeFacTo Technologies has become the newest member of its In-Sequence Technology Partner Program, promoting EDA interoperability and advanced design methodologies. The first collaboration between the companies is the integration of DeFacTo’s scan insertion tool, to be released later this year, and Sequence’s PowerTheater.
Today, RTL power analysis is performed on designs before most of the DFT logic is implemented. Furthermore, given scan-ready, gate-level netlists, test vectors which are applied post-silicon are generated after synthesis, so power problems are discovered late, leading to unnecessary design iterations. Compared to the gate level, it is known that any design abstraction allows a better reactivity. Running all necessary test vectors on a RTL “scan-ready” design and analyzing power activity pre-synthesis is desirable.
Test logic insertion at RTL by DeFacTo will enable PowerTheater to more accurately analyze power on a scan-ready RTL design. Benefits of this new approach include:
- Detect and solve testability problems very early
- Detect and solve power problems for both testing and functional modes
- Shorten design iterations
- Strengthen design verification at RTL
- Only synthesis and place & route affect test insertion at gate level
- Extend designer’s database including both power and test configurations
- Reuse DFT logic for functional operations such as power-on Reset, contributing to better managed power and timing, and help in minimizing the overall silicon overhead
“By having PowerTheater run its RTL power analysis on ‘scan-ready’ designs, users can avoid unnecessary iterations and achieve greater power efficiency,” said Vic Kulkarni, Sequence president and CEO. “We welcome DeFacTo into the In-Sequence family, and look forward to bringing this new methodology to market soon.”
“Through this collaboration with Sequence, DeFacTo aims to demonstrate that providing scan at RTL contributes in efficiently detecting and solving power problems that become critical during manufacturing testing, and also in better budgeting power in general,” said Chouki Aktouf, DeFacTo CEO and CTO.
DeFacTo Technologies is the latest in a series of In-Sequence partnerships, joining a variety of EDA vendors, foundries, IP providers, design services providers, platform vendors and universities.
About DeFacTo Technologies
DeFacTo is an innovative chip design software company developing breakthrough technology to dramatically enhance the design for test (DFT) process and increase the testability of integrated circuits (ICs) and systems on a chip (SoCs). The company’s mission is to enable designers to plan, analyze, and implement IC test logic before synthesis, by delivering a high quality suite of tools working at the RT level, covering all DFT needs. The company, founded in August 2003, is headquartered in Moirans, France, (near Grenoble) and Palo Alto, Calif.
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence’s power and signal-integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets.