Bluespec to Demonstrate FPGA Implementation of H.264 Video Decoder
Bluespec(TM) Inc., developer of ESL synthesis for control logic and complex datapaths in chip design, will exhibit in stand R38 (Rhodes, Floor 2) during Design Automation and Test in Europe (DATE) 07 at the Nice Acropolis in Nice, France, April 17-19. On display will be a demonstration of a field programmable gate array (FPGA) implementation of an H.264 video decoder designed in nine months with half the lines of code of a pure, non-hardware C-based implementation.
In addition, Gert-Jan Tromp of Dizain-Sync will present his experiences using Bluespec ESL Synthesis to design and synthesize a 1 GHz 130-nanometer multi-port DDR2 memory controller in the DATE Exhibition Theatre at noon Tuesday, April 17.
Finally, Rishiyur S. Nikhil, chief technology officer of Bluespec, will explain Bluespec ESL Synthesis as part of the tutorial titled, “ESL, New Models and Methods to Advance System Level Design.” This tutorial will be in Uranie, Level 3 from 14:30-18:00, Monday, April 16.
About Bluespec
Bluespec Inc. manufactures industry standards-based Electronic Design Automation (EDA) toolsets that significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolsets, the only ones focused on control and complex datapaths, allow ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found by calling (781) 250-2200.
Bluespec and AzureIP are trademarks of Bluespec Inc.
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