Calypto(TM) Design Systems Inc., the leader in sequential analysis technology, announced that its newly introduced PowerPro(TM) CG product that reduces power at the register transfer level (RTL) will support Si2′s Common Power Format 1.0 (CPF).
PowerPro CG extends power-optimization capabilities to earlier stages in the design process. By adding support for CPF in PowerPro CG, Calypto expands the scope of power specification standards. Calypto has joined the Si2′s Low-Power Coalition (LPC) to further work with customers and EDA vendors on improving interoperability between power optimization, design and verification tools.
“Calypto is committed to supporting emerging standards and will continue to work towards ensuring interoperability with other EDA products,” said Devadas Varma, chairman and founder of Calypto.
“As standards develop and evolve, it is critical for new EDA tools to support those standards to ensure interoperability. As the ecosystem for power-aware tools grows, a common interface becomes more important to enable broad market adoption,” says Steve Schulz, president and chief executive officer of Si2. “We welcome Calypto as a member of the LPC and look forward to working with them as the coalition makes new advances in power-aware design flows.”
“Cadence is pleased to collaborate with Calypto on the most advanced solutions for low power design,” said Jan Willis, senior vice president of Industry Alliances at Cadence. “As an advisory member of the Power Forward Initiative, Calypto’s contributions to the development of CPF and their proactive support of pan-industry tool interoperability are greatly appreciated.”
PowerPro CG (for Clock Gating) dramatically reduces power consumption by applying advanced sequential analysis techniques to identify micro-architectural changes that result in a lower-power circuit. PowerPro CG reduces design power by up to 60% with no impact on functionality, area or performance.
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email: firstname.lastname@example.org.
Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc.