Virage Logic Corp. (NASDAQ:VIRL), the semiconductor industry’s trusted IP partner and pioneer in Silicon Aware IP(TM), and TSMC (TSE:2330) (NYSE:TSM), the world’s largest semiconductor foundry, announced that Virage Logic has delivered the industry’s first silicon proven memory for TSMC’s 65-nanometer (nm) general-purpose plus (GP) process.
Virage Logic’s robust and production-tested High-Density (HD) SRAM meets the stringent density, performance and leakage requirements of System-on-Chip (SoC) designers moving to 65nm, allowing them to capitalize on the cost advantages they seek at advanced process nodes.
As process nodes become more complex, it is essential to IP robustness that the silicon be validated in real world conditions. With the new STAR Test Chip based on Virage Logic’s Silicon Aware Self-Test and Repair (STAR) memories, designers can now simulate real world SoC environments because the chip enables both high-speed and low-speed coverage, and employs high memory densities to replicate conditions that produce yield challenges in production volumes.
“The availability of Virage Logic’s silicon proven memory on TSMC’s 65nm GP process will facilitate the market’s migration to smaller process nodes,” said Fu-Chieh Hsu, vice president, design and technology platform at TSMC. “Customers will benefit from our collaboration on the STAR Test Chip because they will realize improved yields at 65nm.”
Through their collaboration at 65nm, Virage Logic, TSMC, and their mutual customers have raised the bar on silicon validation at advanced process nodes by creating the STAR Test Chip validation process that provides designers with silicon verification under real-world conditions.
In addition, the STAR Test Chip architecture achieves advanced yield and repair analysis across process windows, ensuring the most rigorously tested SRAM for consumer, telecom and networking communication applications. The STAR Test Chip validation process established at 65nm provides a silicon proven methodology for TSMC and Virage Logic to work together to develop silicon proven IP for future technologies.
“Virage Logic is committed to providing its customers with silicon proven IP at advanced technology nodes,” said Dan McCranie, president and chief executive officer of Virage Logic. “Being first to market with silicon proven memory IP for TSMC’s 65nm process underscores this commitment and we are very pleased to expand our collaboration on next generation process technology.”
The collaboration between TSMC and Virage Logic showcases how foundries and IP providers can partner to offer SoC designers silicon proven IP on advanced process technologies. The sub-90nm collaboration model was created to address the complexities of robust SRAM design from bit-cell design to silicon validation. At 65nm, Virage Logic and TSMC pioneered the proprietary STAR Test Chip methodology that helps ensure SRAM robustness in a SoC context for functionality, performance and yield. This experience will provide the foundation for the development of silicon validation of Virage Logic’s Area, Speed and Power (ASAP) Memory(TM) and Self-Test and Repair (STAR) memories, and ASAP Logic(TM) product families for TSMC’s future technologies.
Virage Logic will be participating at the upcoming TSMC Technology Symposiums in San Jose, California at the San Jose McEnery Convention Center on April 10; in Waltham-Boston, Massachusetts at the Waltham-Boston Westin Hotel on April 13; and in Austin, Texas at the Austin Hilton Hotel on April 16, 2007.
About Virage Logic’s 65nm Offerings
Virage Logic’s silicon proven ASAP and STAR High-Density SRAM memory offering at 65nm delivers up to a 60-percent leakage reduction while preserving the gate density benefit inherent in the advanced node. In the domain of ultimate power reduction, the ASAP and STAR Ultra-Low-Power SRAM memories support advanced features such as activity based power control, dual supply, and shut-down.
About Virage Logic
Founded in 1996, Virage Logic Corporation (NASDAQ:VIRL) rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today, as the semiconductor industry’s trusted IP partner, the company is a global leader in IP platforms comprising embedded memories, logic, and I/Os, and is pioneering the development of a new class of IP called Silicon Aware IP(TM). Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic’s highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company uses its FirstPass-Silicon(TM) Characterization Lab for certain products to help ensure high quality, reliable IP across a wide range of foundries and process technologies. The company also prides itself on providing superior customer support and was named the 2006 Customer Service Leader of the Year in the Semiconductor IP Market by Frost & Sullivan. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide.
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan.