Aldec Expands in Japan with New Office

Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the opening of Aldec-Japan K.K. headquartered in Tokyo, Japan. The office will provide direct sales and support for all Aldec software and hardware verification products in Japan.

“The new office is our response to the continued growth in verification opportunities we are seeing in the Japanese market. Aldec’s commitment to quick service and high tool quality continues to meet Japanese expectations,” stated Dr. Stanley Hyduke, CEO of Aldec, Inc. “As Aldec grows, the direct physical presence to support our customers with their growing verification challenges was required.”

Products and Support Available:

  • Active-HDL(TM) – complete graphical design entry and mixed language verification solution for Windows operating system. Language Support: VHDL, Verilog, SystemC and SystemVerilog.
  • Riviera-Pro(TM) – mixed language verification solution for 32/64 bit operating systems (Windows, Linux or Unix). Language Support: VHDL, Verilog, SystemC, SystemVerilog, Assertions (PSL and SVA) and Linting design rule checking.
  • HES(TM) (Hardware Embedded Simulation) – unified debugging acceleration solution based on PCI Express hardware acceleration board. Supports: Acceleration, Emulation and Prototyping.

Aldec-Japan K.K. Location:
Four Seasons Building
8F, 2-4-3 Shinjuku
Shinjuku-ku, Tokyo Japan
Japan Website

About Aldec
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for Unix, Linux, and Windows platforms.

Active-HDL, Riviera-Pro and HES are trademarks of Aldec, Inc.