EDA Vendors to Develop Interoperable PCell Library for AMS Design

Five electronic design automation (EDA) companies announced an agreement to collaborate on the creation and distribution of an interoperable PCell library (IPL). The IPL supports the OpenAccess database from the Silicon Integration Initiative (Si2), and is available now as open-source software that any interested party can use. For the first time in semiconductor industry history, an integrated circuit designer will be able to use the same PCell libraries in tools from all five vendors, plus with OpenAccess-based tools from other vendors or universities, or developed in-house.

The five companies involved with the project include Applied Wave Research (AWR(R)), Ciranova(TM), Silicon Canvas(TM), Silicon Navigator(TM) and Synopsys(R). All five companies developing the IPL support the OpenAccess database and are members of Si2. Other companies have been invited to participate, and that invitation remains open to all interested parties.

An IPL has many advantages to semiconductor companies, foundries and EDA vendors. Semiconductor companies will be able to use one common PCell library providing advanced functionality across multiple processes, reducing development and support costs while increasing layout flexibility. Foundries will be able to reduce their PDK development costs while dramatically increasing the number of tools they support. EDA vendors will also be able to reduce PDK development costs, while supporting a wider range of foundry partners.

“One PCell library mechanism supporting multiple tools represents a huge advance for chip designers,” said Steve Schulz, president and CEO of Si2. “The lack of an interoperable PCell solution causes innumerable hours to be wasted translating databases between tools. This IPL will immediately help increase the interoperability of OpenAccess tools, and speed OpenAccess deployment in the semiconductor industry.”

“This is the right thing to do for the industry,” said Walter Ng, senior director of platform alliances at Chartered Semiconductor Manufacturing. “At Chartered, we have long advocated openness and interoperability as a means of best serving our customers and the industry as a whole. This IPL project demonstrates how a single library can support multiple tools equally, and this should lead to overall lower costs and shorter time to market.”

“As a charter member in this initiative and strong promoter of standards that benefit the industry, we believe the IPL collaboration can help our semiconductor customers,” said Rich Goldman, vice president, strategic market development group at Synopsys. “We see this as an opportunity to truly achieve the promise of an open custom analog environment through OpenAccess.”

“Mentor Graphics(R) supports this effort to provide flexibility for customers, and Ciranova’s use of our industry-standard sign-off DRC tool, Calibre(R) nmDRC, will help ensure that library components are truly interoperable across toolsets and foundries,” said Anthony Nicoli, director of marketing, Design-to-Silicon division at Mentor Graphics. “Users will also be able to apply Calibre’s silicon modeling and yield analysis tools to IPL components to further reduce time-to-market and maximize the yields of PCell-based designs across foundries and other process variations.”

The IPL library with source code is available now for free download from the Ciranova web site.

Ciranova is a trademark of Ciranova, Inc. AWR is a registered trademark of Applied Wave Research, Inc. Mentor Graphics and Calibre are registered trademarks of Mentor Graphics, Inc. Silicon Canvas is a trademark of Silicon Canvas, Inc. Silicon Navigator and RDE Framework are trademarks of Silicon Navigator, Inc. Synopsys is a registered trademark of Synopsys, Inc.