Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Ubicom, a leading developer of communications and media processors and related software platforms, has incorporated the Cadence(R) Encounter(R) Timing System into its overall design flow. The Encounter Timing System has allowed Ubicom to streamline the overall time needed to verify their most advanced designs, enhancing the ability to deliver interactive applications and multimedia content for the digital home.
The Encounter Timing System is the most complete and integrated static timing analysis (STA) environment for faster optimization and signoff verification. With the Encounter Timing System, designers of increasingly complex integrated circuits may gain improved time to market, achieve better productivity, signoff-quality timing and signal-integrity analysis. The same signoff-quality analysis is also integrated within the Cadence SoC Encounter(TM) RTL-to-GDSII system for digital implementation processes.
The Encounter Timing System was selected by Ubicom for its ability to provide a consistent view of timing throughout the design flow while accounting for crosstalk, IR drop, electromigration, and thermal and systematic manufacturing variability effects. To get a true sense of timing, design tools must concurrently account for these interdependent effects during physical implementation, not waiting until the later stages of the design flow.
“Today’s nanometer designs face severe technological challenges caused by increasing design size and performance, as well as process complexities,” said Jon Gibbons, vice president of Engineering at Ubicom. “It was important for us to have a signoff solution for our ASIC flow that would accurately address the inter-dependencies of signal integrity, power, and timing. We were impressed that the Encounter Timing System brought all this together in a single solution and will fit seamlessly into our existing flow. Given all alternatives in the market, we believe the Encounter Timing System is the best and most complete signoff solution.”
“The Encounter Timing System clearly answers the unmet needs for a complete signoff analysis and the direct integration within design implementation process for nanometer design closure,” said Dr. Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. “It offers customers the utmost in signoff accuracy, performance, and productivity for today’s most complex designs, which is why it is being embraced by foundries, ASIC providers, and leading fabless semiconductor companies.”
A ubiquitous technology within the Cadence Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution, Encounter Timing System is available in L and XL offerings.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence and Encounter are registered trademarks, and SoC Encounter and the Cadence logo are trademarks, of Cadence Design Systems, Inc. in the United States and other countries.