Altos Design Automation Inc. announced its characterization products Liberate and Variety have been adopted by STARC, the Japanese Semiconductor Technology Academic Research Center. STARC is developing a manufacturing-aware design methodology named STARCAD-CEL that addresses the challenges of very advanced process technologies including 65nm, 45nm and 32nm.
The STARCAD-CEL design methodology will be shared amongst the top Japanese semi-conductor companies that comprise STARC’s membership as a standard digital design platform. Within this flow, STARC will use Liberate to create libraries for design implementation including ECSM and CCS timing, noise and power views. Variety will be used to build libraries for statistical timing analysis (SSTA) signoff.
Nobuyuki Nishiguchi, vice president and general manager at STARC said, “Fundamental to any digital implementation design methodology is the cell library that encapsulates the underlying electrical characteristics of the target process technology.”
Nishiguchi continued, “We selected the Altos products because of their remarkable performance and their ability to support multiple vendors flows especially for statistical timing models. These are essential to manage variation at 45nm and below.”
“STARC performs a very thorough evaluation of every component that comprises their STARCAD-CEL design methodology,” said Jim McCanny, Altos CEO, “To have our products selected by STARC represents a major milestone in Altos’ short history and represents validation of our technology and roadmap. Quality library models, generated with high efficiency, are vital to maximizing the potential of advanced ultra nanometer silicon process technology.”
Liberate is an ultra fast library creator that generates electrical models in Libertytm format. Liberate supports all the latest models for timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective Current Source Models). Liberate also supports low power design styles that include power gating cells, state retention registers and level shifters.
Variety characterizes models for multiple SSTA tools. These include nominal timing information plus additional data representing the impact of any number of parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances. Variety can characterize for both systematic and random variation including linear and non-linear effects.
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield. Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056.