Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the immediate availability of the industry’s first 533 Mbps Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) controller Intellectual Property (IP) core supporting a Low-Cost Field Programmable Gate Array (FPGA) family. This DDR2 SDRAM IP core is optimized for Lattice’s award winning LatticeECP2(TM) and LatticeECP2M(TM) low-cost FPGA families, as well as its high-end LatticeSC(TM) Extreme Performance(TM) FPGA family.
“Lattice is continually redefining the way FPGA designs are implemented by providing features in its Low-Cost FPGAs that typically are found only in high end, more expensive FPGAs from our competitors,” said Stan Kopec, Lattice corporate vice president of marketing. “With the introduction of this 533 Mbps DDR2 IP core for the LatticeECP2 and LatticeECP2M FPGA families, we now provide the highest possible data rate on a Low-Cost FPGA. In fact, today we are up to two speed grades faster than comparable solutions in competitive low-cost architectures. Once again, Lattice delivers ‘More of the Best’ design solutions.”
DDR2 SDRAM Controller IP Core
The DDR2 SDRAM Controller IP core interfaces seamlessly with industry standard DDR2 SDRAM memory devices and has been performance-tuned for Lattice FPGAs. Not only does this IP core support all DDR2 commands, it also is extremely flexible, with intelligent bank management to minimize active commands, a synchronous implementation for reliable operation and a command pipeline to maximize throughput. The most common memory configurations are supported through a combination of variable address widths for different memory devices, programmable timing parameters, byte level writing through data mask signals and burst termination.
A primary feature of the LatticeECP2 and LatticeECP2M architectures is their pre-engineered, high performance parallel I/O that supports generic LVDS standards at speeds up to 840 Mbps. By leveraging the FPGA fabric capabilities, the DDR2 SDRAM Controller IP core is able to interface at a speed of 266 MHz, resulting in a data rate of 533 Mbps: an industry first in a low-cost FPGA architecture.
The DDR2 SDRAM controller is an IPexpress(TM) User Configurable IP core. The IPexpress design flow, included as a standard feature in Lattice’s ispLEVER(R) design tool suite, allows designers to configure the core, generate netlists and simulations files, and evaluate the core in hardware before purchase. More detailed information about the IP core can be found online. To download a full, free evaluation version of the DDR2 SDRAM IP core, please go to the Lattice IP Server tab in the IPexpress Main Window.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP2, LatticeECP2M, LatticeSC, Extreme Performance, IPexpress, ispLEVER and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.