Aldec, Actel Debut CoVer Co-verification Solution for ARM-based FPGAs

Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the release of CoVer(TM), a Windows(R)-based hardware/software co-verification solution, for Actel Corporation (Nasdaq: ACTL). Easing hardware and software integration for engineers using Actel’s field-programmable gate arrays (FPGAs) with an ARM processor, such as Actel’s CoreMP7 soft ARM7(TM) core, CoVer provides control and visibility across engineering teams, which translates into shorter design schedules and lower project costs.

“CoVer is the only product on the market offering hardware-accelerated HDL simulation environment for hardware designers and high-speed prototyping-like debugging for software developers, bridging the gap between system-on-chip (SoC) engineers,” stated Dr. Stanley Hyduke, president of Aldec, Inc. “This approach delivers fully synchronized debugging functionality of peripherals, ARM processors embedded in Actel devices and memories from tools like Active-HDL mixed-language simulator and a commonly used GDB debugger.”

Jake Chuang, senior director, application solutions marketing at Actel, said, “As more and more designers utilize industry-standard ARM processors in FPGAs, the abundance of software and support available, such as Aldec’s innovative CoVer hardware/software co-verification solution, enables designers to get system-level products to market quickly and reduce cost and risk.”

System Performance
Utilizing Aldec’s patented Smart Clock technology to enable fastest hardware verification and on-demand debugging, the CoVer technology is based on using two clock sources: an HDL simulator generated clock (sw clk) and a hardware oscillator generated clock (hw clk). The programmable Smart Clock unit constantly monitors the AHB Bus to identify bus transactions to Custom Peripherals simulated in HDL. Whenever the transaction to the programmed address range is detected, the system clock is switched to the HDL simulator, allowing for debugging of the AHB bus and peripherals. Once the transaction is completed, the clock is switched back to the hardware oscillator enabling processor debugging with a speed of prototyping solutions.

Hardware in-the-loop
The CoVer solution integrates the Active-HDL simulator with the board. The CoreMP7 processor memory and standard peripherals reside in Actel’s ARM-enabled M7A3P1000 ProASIC3 FPGA on the board. Aldec’s patented sw/hw interfacing allows for the simulation and debugging in Active-HDL waveform viewer. The board is connected to the workstation through 32/64 bit to 33/66MHz PCI slot, providing ease of use and high performance. Reprogrammable through PCI or JTAG, the reusable CoVer board can be used for any CoreMP7-based embedded design.

The CoVer solution provides engineers with a complete HW/SW co-verification toolset:

  • Aldec Active-HDL (Designer Edition) mixed-language simulator
  • Actel’s CoreConsole IP Deployment Platform
  • Actel Libero(R) Integrated Design Environment (IDE) – Gold edition
  • Reusable FPGA-based prototyping board with Actel’s ARM7-enabled ProASIC3 FPGA and CoreMP7 soft ARM7 core
  • Software development system, including Actel’s SoftConsole program development environment

CoVer for Actel is available today for $4,995 and includes Active-HDL (Design Edition) mixed VHDL and Verilog, CoVer HW/SW co-verification software and the Actel Libero integrated design environment. All licenses are for one year and can be purchased from Aldec directly or from an authorized distributor

About Aldec
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms.

About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655.

CoVer and Active-HDL are trademarks of Aldec, Inc.