Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the release of Riviera 2007.02, a 64-bit mixed-language design simulation environment handling VHDL, Verilog, SystemVerilog, and SystemC designs. Riviera delivers industry proven simulation performance and accuracy for all multi-million gate HDL designs.
“Aldec continues to gain momentum in the ASIC verification market and with the introduction of Altera Stratix(R) III and Xilinx Virtex(R)5 there is a requirement for 64-bit processing and very large amounts of memory to process the designs. Our customers have requested design simulation support based on 64-bit architecture,” stated Dr. Stanley Hyduke, President of Aldec, adding, “We responded with Riviera, a 64-bit simulator that supports mixed HDL simulation and debugging, enabling our customers to have continued success in validation of their large IC devices.”
The densities of ASIC and new FPGA devices demand design verification flows that can utilize the latest multi-core 64-bit processor machines. Riviera, running in a true 64-bit mode, leverages the hardware to perform large simulation runs requiring 16 gigabytes of memory.
To further reinforce a designer’s control over the quality and speed of design verification, Riviera 2007.02 includes performance optimization for RTL and gate level simulation (1.5-2x speed improvements over the previous release), VHDL and Verilog expression coverage, mixed PSL assertion with VHDL and Verilog design blocks support, and graphical debugging tools designed specifically for large IC designs.
Pricing and Availability
Riviera 2007.02 is available today and is sold directly from Aldec and its authorized world-wide distributors. Get a FREE evaluation copy of Riviera 2007.02.
Aldec, Inc., established in 1984, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux, Solaris and Windows platforms.
Riviera is a trademark of Aldec, Inc.