ArchPro Design Automation announced significant enhancements to its multi-voltage design tool lineup – MVSIM, for verification of power-managed designs; MVRC: a voltage rule checker; and MVSYN: automating the implementation of multiple voltages.
Significant technology and ease-of-use upgrades for ArchPro’s products include:
- 2x capacity improvement to handle large SOCs in 65nm and 45nm – ArchPro is seeing some of the largest designs in the industry, > 200M transistors
- New architectural constructs to handle the complexity of leading-edge, low-power designs, with 100s of islands and/or complex power management protocols
- Keeping up and ahead of design practices of 45/32nm
- Platform for better integration into 3rd party tools with Tcl interface to database, including a Tcl API for database queries
- Front-end integration with the industry’s leading parsers from Verific to provide comprehensive multi-language support
- Neutral platform for support of emerging standards, i.e. UPF and CPF – customers can still use best-in-class tools in their flows without worrying about formats
- User customizable multi-voltage rules allow companies to establish baseline low-power flows
ArchPro customers are aggressively designing and verifying some of the most sophisticated low-power architectures, with chip sizes exceeding 200M transistors with more than 20 voltage domains. They also use very advanced low-power methodologies such as Power Gating and Dynamic Voltage Frequency Scaling.
Designs with less than three voltage islands can be handled with conventional flows and extensive scripting, but as the number of islands grows, the challenges of the complex relationships between the islands require sophisticated solutions such as those from ArchPro to verify and manage these islands properly.
ArchPro provides EDA products to meet low-power and multi-voltage power management challenges facing SOCs at 90nm and below. Having launched many of the world’s first EDA products for power-managed, multi-voltage, low-power design environments that allow for design simulation, verification and implementation prior to silicon spins, ArchPro is paving the way toward reducing cost, risk, and time to market for chip designers. ArchPro is an ARM(R) Connected Community member as well as Si2 Low Power Council member. Privately held ArchPro is based in San Jose, Calif.