Toshiba Unveils Package-on-Package Memory Components for Handsets

Toshiba America Electronic Components, Inc. (TAEC) announced availability of high-capacity memory solutions using Package-on-Package (PoP) technology, a multi-chip packaging technique that enables significant circuit board space savings in cellular handsets by stacking a high-density memory component on top of the processor so the two components require only one footprint on the board.

The initial PoP offering developed by Toshiba Corp. (Toshiba) includes 14mm x 14mm and 15mm x 15mm packages. The 15mm x 15mm devices are fully compliant with the JEDEC standard, and will support the Marvell(R) PXA3xx family of application processor, as well as other processors compatible with the JEDEC standard. The 14mm x 14mm packages are compatible with other popular processor configurations.

“As a leading supplier of MCP memory solutions for cellular handsets, the addition of PoP technology is a notable development that supports our cellular handset customers’ design requirements for thinner, smaller phones by significantly reducing board space,” said Scott Beekman, Senior Business Development Manager, Mobile Memory Products, for TAEC. “The adoption of PoP technology is gaining momentum, and we are supporting the two most widely-used package configurations.”

“We have been working closely with Toshiba during development of our next-generation Monahans processor, which will feature PoP capability,” said Gary Forni, Director of Platform Enabling, Cellular and Handheld Business Unit, Communications and Consumer Business Group at Marvell(R). “Toshiba’s PoP memory solutions, which support NAND flash and Low Power DDR, combined with Marvell’s PXA3xx family of application processors, will provide our customers with a ready-to-use, space saving solution.”

In a cellular handset PoP configuration, two Ball Grid Array (BGA) packages are stacked vertically. The bottom package, typically an applications processor, has the usual array of metallic balls, or bumps, on the underside. In addition, it also has an array of footprints (lands) on the upper surface that are designed to match a compatible BGA package, typically a multi-chip memory BGA, which is soldered on top. Standardized layouts for the BGAs enable signals to be routed between the two components.

While a wide range of memory components can be selected for a PoP memory BGA, typical configurations today include 512Mb(1) to 1Gb(2) Low Power SDRAM and up to 2Gb of NAND Flash. Due to height limitations in thin mobile phones, typically a maximum of three or four memory die are packaged in memory PoP components today. Mobile phones increasingly offer advanced multimedia functions, such as high resolution cameras and music players, but real usability also requires larger memory capacities able to store high resolution digital photos, video and hours of music. This is driving demand for high-density memory solutions that significantly reduce footprints on the board.

Key specifications for Toshiba Memory PoP

  • Product: PoP multi-chip memory components that stack two, three or four memory die
  • Memory Options (today): 512Mb or 1Gb Low Power SDRAM, 512Mb, 1Gb or 2Gb NAND Flash
  • Power supply voltage: LP SDRAM: 1.7 – 1.9V, NAND Flash: 1.7 – 1.95V
  • Compatible standard: JEDEC standard for 15mm x 15mm package
  • Exterior dimensions: 14.0mm (W) x 14.0mm (L) (Memory BGA only), 15.0mm (W) x 15.0mm (L) (Memory BGA only)

Initial configurations of Toshiba memory PoP technology are sampling now, in 14mm x 14mm (152 ball) and 15mm x 15mm (160 ball) package sizes, with a 0.65mm ball pitch. Package height for the memory PoP depends upon number of die encapsulated. As these are semi-custom devices, pricing is dependent on the memory configuration selected.

About Marvell Technology Group Ltd.
Marvell (Nasdaq: MRVL) is the leader in development of storage, communications and consumer silicon solutions. Marvell’s diverse product portfolio includes switching, transceiver, communications controller, wireless, and storage solutions that power the entire communications infrastructure, including enterprise, metro, home, and storage networking. As used in this release, the term “Marvell” refers to Marvell Technology Group Ltd. and its subsidiaries, including Marvell Semiconductor, Inc. (MSI), Marvell Asia Pte Ltd (MAPL), Marvell Japan K.K., Marvell Taiwan Ltd., Marvell International Ltd. (MIL), Marvell U.K. Limited, Marvell Semiconductor Israel Ltd. (MSIL), RADLAN Computer Communications Ltd., and Marvell Semiconductor Germany GmbH. MSI is headquartered in Santa Clara, California, and designs, develops and markets products on behalf of MIL and MAPL. MSI may be contacted at 408-222-2500.

About TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes memory and flash memory-based storage solutions, a broad range of discrete devices, displays, medical tubes, ASICs, custom SOCs, microprocessors, microcontrollers and wireless components for the computing, wireless, networking, automotive and digital consumer markets.

TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba Corp. (Toshiba), Japan’s largest semiconductor manufacturer and the world’s fourth largest semiconductor manufacturer. In more than 130 years of operation, Toshiba has recorded numerous firsts and made many valuable contributions to technology and society. For technical inquiries, please e-mail

Marvell(R) is a trademark of Marvell.

(1) When used herein in relation to memory density, megabit and/or Mb means 1,024 x 1,024 = 1,048,576 bits. Usable capacity may be less. For details, please refer to specifications.
(2) When used herein in relation to memory density, gigabit and/or Gb means 1,024 x 1,024x 1,024 = 1,073,741,824 bits. Usable capacity may be less. For details, please refer to specifications.