Sequence Debuts SMMART Macro Modeling using Advanced Region Technique

Sequence Design, EDA’s power-aware SoC design technology leader, announced a range of new features for CoolTime and CoolPower, including breakthrough SMMART (Sequence Macro Modeling using Advanced Region Technique) technology for advanced modeling of memories and other macros for SoC dynamic voltage-drop analysis. SMMART provides highly accurate representations of macros for chip-level analysis, with no capacity limitations.

Macros pose a special challenge due to their internal physical and logical complexity and other difficulties associated with their size, and SMMART addresses these challenges with its temporal and spatial modeling. Other transistor-based solutions fail due to sheer data size, prohibitive runtimes, and memory footprint at the SoC level.

“The low-power design closure challenge requires smarter and better tools, particularly with the rapid advance toward 65nm,” said Vic Kulkarni, Sequence president and CEO. “With memories being an increasing cause of dynamic voltage drop-related silicon failures, key customers and foundry partners deploying Cool Products worked with us in understanding and solving the memory modeling issues at 65 nm and beyond.”

CoolTime extends its unique concurrent voltage-aware timing analysis capability with advanced and accurate voltage selection. Designs pushing performance limits can now reduce pessimism by precise selection of instance voltages. Performance improvements include a 40 percent reduction in memory footprint and runtime for dynamic voltage drop analysis, and a 10X improvement in disk usage for dynamic voltage drop optimization. In addition, hold time optimization algorithms now insert up to 20 percent fewer buffers to limit ECO changes, speed design closure, and reduce power.

According to Don Butler, vice president of engineering for Genesis Microchip: “We have seen successful silicon after using CoolTime to insure our power-grid integrity for dynamic voltage drop and connectivity. The new CoolTime release improved our throughput by 30 percent and also reduced the memory usage by 30 percent.”

About Cool Products
Sequence’s Cool Products family – CoolTime, CoolPower, and CoolCheck – cut design closure times by preventing time-consuming iterations between separate timing, SI, power analysis and optimization tools. CoolTime, the industry’s most accurate dynamic voltage drop analysis and optimization solution, concurrently analyzes timing, signal integrity, static IR drop, and electromigration. CoolPower includes automated power, timing, and signal integrity optimization features. Both leakage and dynamic power can be automatically optimized using CoolPower’s multi-Vt cell swapping and cell resizing, and its MTCMOS power gating optimization slashes leakage power up to 100X or more. CoolCheck enables effective power grid debug early in the flow with a fast vectorless technique for finding high resistive connectivity of standard cells and macros.

About Sequence
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence’s power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. Sequence has worldwide development and field-service operations and is privately held.