Lattice Semiconductor (NASDAQ: LSCC) announced it will demonstrate programmable PCI Express design solutions using its LatticeECP2M(TM) FPGA development board at the Embedded World Conference and Exhibition, February 13-15, in Nürnberg, Germany. The LatticeECP2M board was tested at the October 2006 PCI-SIG compliance workshop and was demonstrated to be fully PIC Express v.1.0a specification compliant. The Lattice exhibit is located in Hall 12, Stand 674.
The LatticeECP2M FPGA family has been named “Product of the Year” by Electronic Products magazine: it is the only low-cost FPGA family to offer both DSP functionality and SERDES I/O, as well as a host of features and performance that are unprecedented in a low-cost device.
Lattice also will demonstrate how to use the pre-engineered I/O components within the LatticeECP2M FPGA family to implement the “7:1″ source synchronous LVDS (Low Voltage Differential Signaling) interfaces commonly found in display applications.
About LatticeECP2M FPGAs
LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low-cost SERDES capability for chip-to-chip and small form-factor backplane applications. The LatticeECP2M family maintains all of the compelling features of the 90nm LatticeECP2(TM) family that are required for high-volume, cost-sensitive applications, while dramatically increasing memory capacity (ranging from 1.2 Mbits to 5.3 Mbits) and DSP resources (ranging from 24 to 168 multipliers).
The five devices in the series, ranging in size from 19K to 95K lookup tables (LUTs), provide an inexpensive alternative for implementing PCI Express, Ethernet, Serial RapidIO and CPRI/OBSAI interfaces. The SERDES integrated into the LatticeECP2M devices has been engineered as a quad-based architecture with 1 to 4 quads (up to 16 SERDES channels maximum per device), depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels), and each SERDES channel operates on just 100mW at full speed and supports data rates from 270 Mbps to 3.125 Gbps.
A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today’s most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP2, LatticeECP2M and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.