Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that 3Leaf Networks, a leader in scalable enterprise data centers and virtual servers, has incorporated the Cadence(R) Incisive(R) Formal Verifier (IFV) into its overall design flow for assertion-based formal analysis. With this Cadence technology, 3Leaf Networks’ logic design teams will introduce assertions into the verification process and begin formal verification early in the design process. This will allow 3Leaf Networks to increase its design verification throughput and improve design quality on its complex control blocks by enhancing and streamlining its previous simulation-only verification process.
After initial evaluations of IFV, 3Leaf Networks realized that its logic designers were performing verification weeks or even months prior to simulation. By working closely with Cadence they were able to get up and running much earlier than predicted, and establish reusable assertion-based verification methods across formal analysis and simulation that has become the foundation for design team verification.
“As new users of the Incisive Formal Verifier technology and assertion-based verification, we were somewhat surprised to see such dramatic quality and schedule improvements,” said Bob Quinn, CEO, 3Leaf Networks. “Recent complexities have been seriously testing the capabilities of simulation alone. IFV brought on a new way of thinking about verification by offering an easy path for our designers to get involved in the process, with the ability to find bugs much earlier.”
Part of the Cadence Logic Design Team Solution, Incisive Formal Verifier provides an efficient way to perform early verification. The technology exposes most functional bugs early in the development of the design, including complex corner-case bugs and protocol compliance violations, while also verifying problem-prone areas. Other technologies from the Logic Design Team Solution in use at 3Leaf include Incisive(R) Design Team Simulator, Encounter(R) RTL Compiler, Encounter(R) Conformal(R) Equivalence Checker, and First Encounter.
“We know how important it is for our customers to get their logic design teams involved in the verification process,” said Mitch Weaver, corporate vice president, Verification Division, Cadence Design Systems, Inc. “Our successful IFV solution is quickly becoming the cornerstone of design team verification by offering an easy to adopt methodology, resulting in improved project schedules and greater predictability.”
More info: 3Leaf Networks’ success with IFV
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence(R) software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Incisive, Encounter and Conformal are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems in the United States and other countries.