YOGITECH announced fRMEM, a family of fault supervisors for memory subsystems fulfilling the risk level SIL3 in accordance with IEC 61508 as certified by TÜV SÜD. fRMEM is available for SRAM connected to the system bus, for Tightly Coupled Memories, caches and for non volatile memories (Flashes, NAND Flashes and EEPROM). fRMEM is also designed to allow interoperability with external Built-In-Self-Test or Built-In-Self Repair modules.
Fault detection in memories is typically addressed by using Error Detection and Correction Codes (EDC or ECC), but several limitations are inherently embedded in EDC/ECC being used as a standalone approach.
Standard EDC/ECC itself is not allowing SIL3 compliance for a memory subsystem composed by the memory array, the memory controller and the protection circuitry; EDC/ECC has a meaningful impact in terms of area and timing overhead; for large memories, multiple faults cause protection degradation; from a system point of view, EDC/ECC is not a solution for faults caused by unintentional or forbidden accesses.
fRMEM is an IP providing on top of EDC/ECC a set of proprietary techniques to fulfil the limitations of a pure EDC/ECC based solution thus leading to a meaningful step forward in the state-of-the-art implementation, for example, of automotive safety-critical systems in chassis and passive/active safety as braking control, ABS, ESP.
SIL3 compliance is ensured by an enhanced protection and a self-checking architecture for the supervision circuitry itself.
Area overhead is tunable with the Two-memory Architecture, allowing a flexible partitioning of data in pages with selectable protection levels.
Timing overhead introduced by EDC/ECC is prevented by the Fast-track technique, enabling the highest operating frequency with no modification either of the CPU logic or of the memory controller.
The Scrubbing technique, a low-power background running task scanning the memory, maintains the protection level decreasing the Failure In Time (FIT) by catching silent faults. The Distributed MPU provides a local memory protection tackling HW and SW system-level faults.
“We are pleased and proud to finalize into a product our long lasting R&D activity and strong background in fault detection and fault avoidance techniques.” said Silvano Motto, CEO of YOGITECH. “fRMEM is the first IP in our faultRobust technology roadmap: further IPs protecting CPUs, busses and peripherals are in an advanced stage of development and will be introduced in the market during 2007 extending meaningfully our SIL3 compliant IP portfolio for automotive safety-critical systems. YOGITECH is going to play a key role in enabling solutions in accordance with IEC 61508 standard and related derivatives applied to System-on-Chip conception and design.”
“Nowadays traditional safety related systems are increasingly substituted by programmable electronic systems. The failure of these systems could cause tremendous hazards.
The functional requirements to these programmable electronic systems are rising steadily hence requiring a more complex processing, which besides has to be safeguarded.” said Frank Rauch, Program Manager of Electronic Systems, TÜV SÜD Automotive GmbH.
“The use of architectures based on multiple hardware channels is a commonly adopted approach to match the risk level SIL3 in accordance with IEC 61508.
However, the unknown Common Cause Faults (CCF) failure rate decreases such architectures into an insufficiently protected single channel.
YOGITECH faultRobust technology is a step forward tackling this inherent limitation and we are glad to continue our activity aimed to certify the compliance of faultRobust IPs and related methodologies to the IEC 61508 standard.”
“The fRMEM architecture provided by YOGITECH will enable NXP Semiconductors to deliver attractive automotive microcontrollers with SIL3 memory protection capability.” said Toni Versluijs, Business Development Manager Invehicle Network Controllers of NXP Semiconductors. “This is NXP Semiconductors’ first step towards automotive microcontroller solutions based on a single processor core for high availability and/or safety critical ECUs. These single processor controllers will enhance ease of use, increase the intrinsic robustness and reduce the silicon area for SIL3 solutions.”
YOGITECH is a company with proven experience in System-on-Chip (SoC) , Mixed-Signal design & verification, and fault-tolerant integrated circuits. YOGITECH offers a catalogue of eRM Verification Components to shorten time-to production of Intellectual Property cores and SoC designs based on standard protocols such as OCP, ATAPI, CAN and LIN. Additionally, YOGITECH offers the Analogue Mixed-Signal Verification Kit (AMS vKit), a unique solution for the verification of mixed-signal circuits and systems. Today, world leaders in the semiconductor industry rely on YOGITECH’s verification solutions and services.