ASSET(R) InterTech, Inc., an international leader in boundary-scan (JTAG/IEEE 1149.1) test and in-system programming (ISP), has opened the industry’s first Design-for-Test (DFT) Lab for validating the JTAG infrastructure in chip and printed circuit board designs.
The lab will offer a free analysis of pre-prototype designs and advice to ensure that the JTAG infrastructure can be effectively deployed in its traditional structural test applications as well as in advanced applications that take advantage of the JTAG infrastructure.
“Today there are several test and programming methodologies which depend upon an effective boundary-scan infrastructure. Without a properly designed JTAG infrastructure, these advanced methodologies can’t perform their functions,” said Arden Bjerkeli, ASSET’s director of support. “Quite often, design or verification engineers are not familiar with some of the finer points of JTAG design-for-test. The DFT Lab can strengthen the JTAG infrastructure in chip and circuit board designs before samples or prototypes are ever produced. That means that development and production schedules can be maintained and expensive re-designs following prototype production will be avoided.”
ASSET’s first DFT Lab is located in Silicon Valley at 2033 Gateway Place, Suite 600, San Jose, CA 95110. The services of the lab are available to first-time users of boundary scan. Scott Creekpaum has been named manager of the lab. The free analysis and design recommendations will be performed with ASSET’s DFT Analyzer(TM), the industry’s only tool that automatically verifies the JTAG testability of board designs. The accuracy of a chip design’s Boundary-scan Description Language (BSDL) file will be verified with the BSDL Validation Service, a collaborative effort of ASSET and Agilent Technologies, Inc. In addition, other tools can be applied to board and chip designs to validate their JTAG capabilities.
About ASSET InterTech
ASSET InterTech, Inc. develops, markets, sells, and supports boundary-scan design tools, test technology and in-system programming (ISP) products worldwide. ASSET’s ScanWorks(R) test system and the DFT Analyzer(TM) circuit board design tool are affordable, easy-to-use and powerful. For product information, call toll free 888-694-6250, send faxes to 972-437-2826, direct e-mail to firstname.lastname@example.org.