Taking the final step in the quest for dual metal gates, SEMATECH engineers have demonstrated high-k/metal gate stacks that were used to build high-performance nMOS and pMOS transistors in a CMOS configuration.
This breakthrough removes the obstacles to commercial implementation of high-k metal gate stacks in transistors for the 45 nm and 32 nm technology generations. It also complements the consortium’s identification last year of effective nMOS materials for metal gates and previous success with developing high mobility high-k dielectrics. The combination of these successes provides a powerful tool for extending CMOS technology.
The pMOS and nMOS materials were successfully integrated into highly scaled CMOS devices that showed low threshold voltage (Vt) similar to conventional polysilicon/SiO2 devices, and ultrathin equivalent oxide thickness (EOT) in the range of 1.0–1.2 nm.
These CMOS devices were fabricated with conventional gate-first, high-temperature processing flows practiced in the industry today, with no reduction to drive currents or other performance metrics. In addition, this good performance was demonstrated without using substrate counter-doping or other extraordinary or complicated measures.
This demonstration paves the way for member companies to integrate the technology into their manufacturing processes. SEMATECH engineers will continue to work to scale this technology for future generations and for further optimization.
Details of the new technology have been transferred to SEMATECH members and will be discussed in future professional settings.
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