Altera Corporation (NASDAQ:ALTR) announced that it is making its Pre-emphasis and Equalization Link Estimator (PELE) technology available through its EDA partners to designers who need to estimate the signal integrity settings in Altera’s Stratix(R) II GX FPGAs. Mentor Graphics Corporation is the first EDA partner to integrate PELE into its tool flow. Originally available only to Altera’s internal signal integrity experts, PELE, combined with Mentor Graphics(R) HyperLynx tools, allows high-speed designers to simulate and predict system performance in a matter of hours; otherwise, verifying performance on a laboratory test bench could take months.
“Integrating PELE into our EDA partners’ design tools is an essential step for customers to accelerate the design of multi-gigabit transceivers and to get a product to market,” said David Greenfield, senior director of product marketing for high-end FPGAs at Altera. “Altera is committed to providing the tools to help our customers develop their next-generation systems in the most productive way possible.”
How It Works
Using a comprehensive model of the Stratix II GX multi-gigabit transceiver, PELE technology uses independently extracted or measured frequency-domain characteristics of the customer’s serial channels to search for the optimal signal-integrity setting estimate for each of the channel characteristics. This eliminates guesswork when determining the optimized signal-integrity settings for Stratix II GX FPGAs, which integrate up to 20 low-power transceivers operating between 600 Mbps and 6.375 Gbps.
“The combination of HyperLynx and Altera’s PELE technology provides our mutual customers with leading-edge tools to design their most advanced systems,” stated Dan Boncella, director of marketing, Mentor Graphics Corporation. “These capabilities enable users to optimize system performance while reducing their design cycle times.”
HyperLynx design tools allow users to extract the frequency-domain S-parameter characteristics of high-speed interconnects from circuit board and backplane layouts, such as the new I-Trac backplane system from Molex Incorporated. The way that Altera’s PELE technology is embedded into Mentor’s design flow ensures file compatibility. PELE directly imports the frequency-domain S-parameter files from HyperLynx or customer measured data, and configures Mentor’s ELDO analog simulator directly, substantially improving productivity and decreasing design risk. Users can then take the Stratix II GX ELDO-model outputs and predict the bit error rate (BER) and eye opening over hundreds of billions of bits in a short period of time.
Learn More at DesignCon 2007
Two papers describing Altera’s and Mentor’s signal integrity tools will be presented at DesignCon 2007, being held from January 29 to February 1, 2007 in San Jose, California. The paper titled “Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution” describes PELE and will be presented at 9:20 a.m. Tuesday, January 30. The paper titled “Pre-Emphasis and Equalization Parameter Optimization With Fast, Worst-Case/Multibillion-bit Verification”, which Altera co-authored with Mentor Graphics Corporation and Molex Incorporated, will discuss a novel, seamless tool flow for signal integrity and will be presented at 9:30 a.m. Wednesday, January 31. To see live demonstrations of Altera’s Stratix II GX FPGA, Mentor’s HyperLynx tools with PELE, and Molex’s I-Trac connector solutions, please visit booth 503, booth 604, and booth 301, respectively.
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