Lattice Semiconductor (NASDAQ: LSCC) announced the FreedomChip(TM) cost reduction methodology for its Extreme Performance(TM) LatticeSC(TM) and LatticeSCM(TM) (“LatticeSC/M”) FPGA families. Customers can reduce the price of selected high volume LatticeSC/M FPGA designs from 30% to 75% by converting to the pin compatible Lattice FreedomChip device with a fully integrated, seamless design methodology.
The FreedomChip methodology is a completely new approach to the challenge of FPGA cost reduction that employs industry standard ASIC techniques to comprehensively test a LatticeSC/M die to the customer’s specific design. Through automatic insertion of scan logic and dedicated silicon test features, the customer’s netlist is implemented in low-cost, custom-tested silicon. This eliminates the difficult and error prone back-end design conversion associated with traditional structured ASICs. The FreedomChip approach is the first FPGA-based design methodology to employ comprehensive scan-based test structures in the fabric specifically to achieve these results. Fault coverage of over 99% typically is achieved using these test techniques for any given design and device.
“The use of proven ASIC test techniques in an FPGA fabric sets FreedomChip distinctly apart from other approaches to FPGA cost reduction,” said Doug Foster, Lattice Director of Test Development and FreedomChip Program Manager. “By utilizing the standard FPGA die as a platform, the FreedomChip methodology is able to provide customers with significantly lower NREs and faster time to market than is possible with ASICs or structured ASICs while maintaining complete timing compatibility.” Timing errors are the number one cause of ASIC and Structured ASIC re-spins, and this trend is expected to worsen on future technologies.
Using the new design methodology, Lattice customers will be able to design, debug and move into production their end-system products using standard LatticeSC/M FPGAs while minimizing design effort and maximizing flexibility as the system design matures. Once high volume manufacturing is needed, FreedomChip equivalents can be ordered from Lattice with a minimum quantity ranging from as low as 1200 to 3600 pieces (depending on device density) delivered in 12 weeks or less.
While the FreedomChip methodology custom-tests the FPGA core and interconnect for the specific design, all I/O and block-level functions (MACO(TM) blocks, SERDES, memory, etc.) remain user-configurable and programmable, allowing additional flexibility to tune design parameters without redesign.
The new FreedomChip cost reduction solution initially will support all LatticeSC and LatticeSCM devices manufactured in flip chip packages. These devices range from the 25K LUT LatticeSC/M25 in the 1020-ball Flip-Chip BGA (fcBGA) to the 115K LUT LatticeSC/M115 in the 1704-ball fcBGA package. All speed grades of each device are supported by the FreedomChip methodology.
Seamless Integration into the Lattice ispLEVER Design Tool Suite
The FreedomChip methodology is integrated into Lattice’s ispLEVERâ software design tool suite — no additional software is required. When using ispLEVER’s FreedomChip mode, necessary logic is added automatically to allow full scan testing, seamlessly and transparently. Using this methodology, the design can be targeted toward both a LatticeSC/M FPGA and a FreedomChip device simultaneously. This means that a design that targets the FreedomChip flow from the outset can be used first on standard LatticeSC/M FPGAs for initial production builds and then replaced with the reduced cost FreedomChip devices for actual production with no additional design work or time required.
Pricing and Availability
The FreedomChip cost reduction methodology is embedded into Lattice’s ispLEVER design tool suite: there is no added cost for the FreedomChip design capability. Lattice’s ispLEVER Version 6.1 Service Pack 2 is being provided to Lattice customers to support initial designs. NRE charges for FreedomChip are $75K for a single design on any device supported. In high volume (>25K pieces), cost reductions compared to the standard LatticeSC/M devices range from 30% per unit for the LatticeSC/M25 to 75% for the LatticeSC/M115. Production volumes of FreedomChip versions of the LatticeSC/M family are scheduled for Q2 2007.
About the LatticeSC/M FPGA Family
The Extreme Performance LatticeSC family is designed to provide unsurpassed performance and connectivity essential for high-speed applications. Fabricated on Fujitsu’s 90nm CMOS process technology utilizing 300mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity.
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8Gbps data rates, PURESPEED(TM) parallel I/O providing industry-leading 2Gbps speed, innovative clock management structures, FPGA logic operating at 500MHz and massive amounts of block RAM. Lattice’s unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks also are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as SPI4.2, Ethernet MAC and PCI Express control functions developed by Lattice to shorten end-system time to market.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), Extreme Performance, FreedomChip, LatticeSC, LatticeSCM, ispLEVER and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.