In response to a Request for Technology issued last week, the Low Power Coalition (LPC) of Silicon Integration Initiative (Si2) announced that Cadence Design Systems has provided full source code for a Common Power Format (CPF) version 1.0 parser to the LPC. The parser, which is TCL based, will enable LPC members to more quickly bring products to market that support CPF, which was approved as a Si2 Specification last week.
“As a member of the LPC, STMicroelectronics is pleased with the rapid progress and approval of the CPF 1.0 Specification, as well as the contribution of the CPF Parser,” says Philippe Magarshack, group vice president, Central CAD and Design Solutions general manager, STMicroelectronics. “The CPF Parser will facilitate the evaluation of the specification and the integration of a coherent low-power design solution for our key applications in cellphone baseband and application processors, connectivity, data storage, and imaging.”
“The CPF parser donation is evidence of the strong technology behind the CPF specification,” said Vic Kulkarni, President & CEO of Sequence Design. “We intend on taking advantage of the CPF parser capabilities as we further develop our leading-edge tools for power-aware SoC designs.”
“Atrenta welcomes the contribution of a CPF parser to the SI2 Low Power Coalition,” said Ajoy Bose, president & CEO of Atrenta. “We are actively participating in driving power standards so our customers benefit from a simple industry-wide low-power design flow. Availability of this reference implementation parser will ease the addition of CPF support to our SpyGlass Low Power and Power Estimation products.”
“With the approval of CPF 1.0 last week, users have spoken and CPF is a reality,” said Jan Willis, senior vice president of Industry Alliances at Cadence. “Now is the time for the industry to converge on one standard through Si2. Our parser submission to the Si2 Low Power Coalition will help accelerate adoption of CPF across the industry.”
“Si2 is pleased with this donation to the LPC as it will allow companies to provide support for CPF in their tools more rapidly,” says Steve Schulz, president and CEO of Si2. “Validation of the concepts embedded in the CPF specification can only be accomplished by deploying tools in real low power design flows.”
The CPF Parser will be available from Si2 to all LPC members.
About the Low Power Coalition (LPC)
The Low-Power Coalition (LPC) will deliver enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability. Members include: Apache Design Solutions; ArchPro Design Automation Inc.; Atrenta; Azuro (UK) Ltd.; Cadence Design Systems, Inc. (NASDAQ: CDNS); ChipVision Design Systems AG; Golden Gate Technology; IBM (NYSE: IBM); Intel Corporation (NASDAQ: INTC); Magma Design Automation, Inc. (NASDAQ: LAVA); NXP Semiconductors; Sequence Design, Inc.; STMicroelectronics (NYSE: STM); Texas Instruments (NYSE: TXN); Virage Logic (NASDAQ: VIRL).
Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world.