CebaTech Inc. launched the first C-to-RTL compiler capable of working efficiently on large, complex designs at a high level of abstraction and then automating the process of creating high-performance hardware solutions. CebaTech’s C2R Compiler enables full-chip designs to be architected, verified, and implemented using ANSI C as the design language in a flow that is two to three times faster than using the traditional RTL-based design approach.
The C2R Compiler generates synthesizable Verilog RTL from untimed ANSI C. Hardware architecture is defined in the C source code, which remains the golden source throughout the design flow. Software engineers working with hardware architects can rapidly create accelerated hardware implementations of software algorithms to meet performance, cost, and power requirements.
CebaTech’s C-based ESL design methodology and C2R Compiler allow fast changes to the system architecture, enabling extensive exploration of design tradeoffs to achieve the optimal design. In addition, the CebaTech flow allows functional verification of the hardware design to be performed in native C software environments, eliminating the dependence on RTL simulation, speeding up the verification process and lowering costs.
Andres Gonzalez, president and founder of Agora Laboratories said: “We’ve been using CebaTech’s C2R Compiler technology to take a legacy G.7xx audio codec, as well as the MPEG-4 video compression algorithm, into hardware. Their extensive support of ANSI C syntax allows us to leverage existing C code bases with minimal changes. The compiler provides the ability to quickly develop FPGA prototypes to demonstrate accelerated hardware solutions to potential clients.”
“The C2R Compiler was invented to consume an enormous, robust, open-source C code base,” stated Chad Spackman, co-founder and CTO of CebaTech. “It was our desire to capture the integrity of that software in hardware and to impose an architecture that would allow the integrity of the design to be verified in a standard C development environment. There were, and still are, no other ESL tools on the market that even begin to attempt this sort of thing. Our compiler has enabled us to create a hardware implementation of the complete TCP/IP stack for 10G applications.”
Price and Availability
The C2R Compiler is available now for FPGA and ASIC designs. U.S. pricing starts at $145,000. For more information, contact firstname.lastname@example.org.
Founded in early 2004 and headquartered in Eatontown, NJ, CebaTech Inc develops ESL tools and intellectual property modules that accelerate the development and realization of software algorithms and complex communication protocols in silicon. CebaTech’s products will include high-value,10G TCP/IP cores for networking, storage, and communication systems and servers as well as ESL technology that transforms SoC/ASIC/ FPGA development into a C-based design process, alleviating existing verification bottlenecks, reducing costs and accelerating time to market. CebaTech is privately held, with venture funding from 2M, SAS and NJTC.