Bluespec Inc., developer of the only electronic system level (ESL) synthesis for control logic and complex datapaths in chip design, said that it has begun volume shipments of its ESEComp, synthesis for SystemC-based hardware design.
System C has been used for transaction-level modeling without an effective path to implementation. Now designers can write very abstract transaction level models, refine them to a transaction-level design and automatically generate register transfer level (RTL) code from there. “RTL implementation is giving way to ESL implementation,” says Shiv Tasker, CEO Bluespec.
Announced earlier this year, ESEComp is the first ESL control logic synthesis software to support the SystemC language. It allows models and designs written at a high-level, including complex control and datapaths, to be generated into efficient RTL code. As a SystemC-based synthesis tool, it unifies architecture modeling, software prototyping and implementation at a high-level of abstraction, and is the only general purpose SystemC synthesis solution bridging ESL and RTL.
There is a free download of the ESL Synthesis Extensions (ESE, pronounced çsç) to SystemC available through Bluespec’s website. This free version supports the ESL Synthesis language extensions for untimed simulations with the standard OSCI SystemC simulator.
ESEComp supports Red Hat Linux operating systems.
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolset, the only one focused on control and complex datapaths, allows ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found by calling (781) 250-2200.
Bluespec is a trademark of Bluespec Inc.