SoftJin, a customized EDA (Electronic Design Automation) software development services company, and Verific Design Automation announced that SoftJin’s Programmable Synthesis Engine (PSE), a logic optimization and mapping software product that is customizable for a variety of programmable platform architectures, has been integrated with Verific’s Hardware Description Language (HDL) component software.
By using individual best in class components from SoftJin and Verific, and pre-verifying those components together, customers get the most value and choose the most appropriate synthesis solution at the most optimal cost.
According to Nachiket Urdhwareshe, SoftJin’s CEO, “We worked with the defacto leader in the HDL front-end component software space, Verific, to integrate their proven HDL front end with our Programmable Synthesis Engine so that our programmable platform customers have access to seamlessly integrated Synthesis solution from RTL onwards.”
Customers can choose from VHDL, Verilog and SystemVerilog input and feed the output of any of these components into SoftJin’s Synthesis engine. On the back end, based on the customizable technology specific optimization and mapping solution built into PSE, the customer can maximize the Quality of Results of the synthesis process by tailoring the mapping and the optimization to its own individual fabric.
“Our companies have the same goal—to provide EDA components for EDA software developers and in-house EDA groups building their own tools,” added Michiel Ligthart, Verific’s chief operating officer. “By working together to integrate Verific’s HDL Front End with SoftJin’s Programmable Synthesis Engine, we are able to offer them a more complete component-based solution that includes the front-end as well as a custom synthesis engine.”
About SoftJin’s PSE
SoftJin’s PSE is a customizable Synthesis engine that allows its users to derive the most from the underlying architecture of a programmable platform. It delivers better Quality of Results (QoR) when compared to traditional FPGA and ASIC synthesis tools. SoftJin customizes each PSE to specific programmable platform architecture and for integration with placement and routing tools. PSE is licensed by programmable platform vendors for use by their customers who are FPGA, ASIC or SoC designers. PSE can also be licensed by system-level EDA companies who would like to extend their offerings into the RTL domain.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL and PSL/Sugar front ends — parsers, analyzers and elaborators — as well as a generic hierarchical netlist database for EDA applications. Verific’s technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: email@example.com.
SoftJin Technologies Pvt. Ltd. develops customized EDA tools for the specific requirements of semiconductor and EDA companies using a combination of EDA software development services and re-usable Building Blocks. SoftJin’s customized EDA software development approach offers the advantages of enhanced EDA software capability, flexible capacity and cost savings to customers. SoftJin has also been recently (Aug 2006) chosen as one of the top 100 private companies in Asia that play a leading role in innovation and technology by Red Herring magazine.
The company’s headquarters are located at Unit No: 102, Mobius Tower, SJR I – Park, EPIP, White Field, Bangalore – 560066, Tel: +91-80-41779999, E-mail: firstname.lastname@example.org
The USA office is located at 2900 Gordon Ave, Suite 100-11, Santa Clara, CA 95051, Tel: (408) 773-1714, Email: email@example.com