DVCon 2007 Reveals Keynote Speaker and Technical Program

The Design and Verification Conference (DVCon), sponsored by Accellera, announced that Moshe Gavrielov, Executive Vice President and General Manager for the Verification Division at Cadence, will be the keynote speaker for the 2007 conference. In addition, the technical program is now available on the DVCon website and advance registration is open. The conference will be held Wednesday, February 21through Friday, February 23 at the DoubleTree Hotel in San Jose, California.

Gavrielov’s keynote, titled “Taking an Enterprise Wide Approach to Next-Generation System-Level Development,” will be presented Thursday, February 22 at 9:00am in the Donner Ballroom.

“We have a very strong program for DVCon 2007 and the number of exhibits has exceeded our expectations,” stated Gabe Moretti, DVCon 2007 General Chair. “We view this conference as an opportunity for attendees to roll up their sleeves and get an in-depth understanding of what the leaders in design and verification are doing. After watching SystemVerilog be absorbed by the design community, we now have one of the first opportunities to hear from actual users about the good, bad and the ugly of using SystemVerilog. Also, people tend to associate design and verification with front-end design only, but we will be expanding the horizons of DVCon by including the physical implementation as well. Physical verification goes hand-in-hand with DFM, which will be a topic of great interest at the DVCon.”

Conference Schedule
DVCon 2007 will have five sponsored tutorials on Wednesday, February 21. The sponsored tutorials are included in the full conference registration fee. For exhibit-only registrants, each tutorial is $50.00.

1. “Pragmatic Plan-Driven Early Logic Design Verification from Formal to Coverage-Driven Simulation and Acceleration” is sponsored by Cadence Design Systems, Inc.
2. “Practical Applications of Mentor’s Advanced Verification Methodology (AVM)” is sponsored by Mentor Graphics Corp.
3. “Pragmatic Adoption of Verification Methodology Manual (VMM) for Re-usable Transaction-Based Test Benches in SystemVerilog ” is sponsored by Synopsys, Inc.
4. “Using Formal Verification to Attain Completeness and Correctness” is sponsored by Denali Software, Inc., Jasper Design Automation, Inc. and Sun Microsystems.
5. “SystemC Transaction Level Modeling Standards and Methodology Guidelines” is sponsored by SystemC.

For information regarding the tutorials, go here.

On Thursday, February 22, in addition to the keynote, the technical program will include four technical sessions followed by the annual “Bigwigs” panel moderated by John Cooley. The Bigwigs panel is open to exhibit-only and full conference registrants. Following the panel, attendees are invited to a reception at 5:00pm that will include all exhibitors.

On Friday, February 23 there will be six additional technical sessions, three embedded tutorials and a panel, titled, “Blended Coverage: A Recipe for Success.” The conference will conclude with the presentation of Best Paper Award.

Exhibits are open Wednesday, February 21 from 4:00pm – 7:00pm and Thursday, February 22 from 4:00pm – 7:00pm. For a list of exhibitors, go here.

Advance registration discount available through January 23. To receive an advance registration discount, register before January 23, 2007. Attendees can register online or can call Nannette Jordan at 303-530-4562.

About DVCon
DVCon is sponsored by Accellera, an industry consortium dedicated to the development and standardization of design and verification languages.