Cadence Design Systems, Inc. (NASDAQ:CDNS), the leader in global electronic-design innovation, said market acceptance of the Cadence(R) VoltageStorm(R) Dynamic Gate (DG) Option power-analysis technology is quickly approaching that of its industry-standard static-power-analysis solution. VoltageStorm DG is a key component of foundry industry reference flows and is used in multiple designs at leading customers such as Sigmatel and OmniVision.
Integrated into the Cadence Encounter(R) digital IC platform for power integrity , power analysis and in-system signoff, the VoltageStorm DG product is also a critical component of the Encounter low-power flow, providing accurate analysis of advanced low-power techniques including power shut-off (PSO), dynamic voltage frequency scaling (DVFS), and multi-supply voltages (MSV).
At Sigmatel, for instance, VoltageStorm DG was critical in isolating and optimizing the interplay of new power-management techniques and packaging parasitics during physical implementation. Sigmatel designs, develops and markets analog intensive, mixed-signal semiconductor solutions for a wide range of digital multimedia products in the consumer-electronics and computing markets.
“We were concerned about the transient peak power during certain modes of operation for our power-sensitive designs,” said Bob Dunnigan, vice president of Design Services at Sigmatel. “We used VoltageStorm DG vector-based analysis to accurately capture dynamic power behavior for specific test patterns during scan and capture mode. We were able to successfully take into account the effect of the de-coupling capacitors and package parasitics during the transient analysis with VoltageStorm, giving us the confidence for our tapeout and making it our golden signoff tool.”
Similarly, OmniVision, which designs and markets high-performance semiconductor image sensors, used VoltageStorm DG analysis for full-chip power management signoff in their advanced low-power design flow.
“Power sensitivity and IR drop analysis are important aspects of advanced low-power imaging designs,” said Sam Huang, director of ASIC Design for OmniVision. “VoltageStorm DG enhances our ability to perform signoff-quality full-chip dynamic IR drop analysis early in the design flow and accurately assess and optimize power delivery and integrity in our designs.”
“In today’s power-sensitive nanometer design environment, both static and dynamic IR drop analyses are necessary to drive signoff-quality results,” said Wei-Jin Dai, corporate vice president of Research and Development at Cadence. “Trying to complete a complex, low-power chip without comprehensive validation of the on-chip power networks is a recipe for failed silicon. VoltageStorm DG allows correct-by-construction signoff during implementation, while leveraging the most advanced low-power-management techniques in use today.”
VoltageStorm static and dynamic IR drop analysis tools are a key component of industry reference flows, including TSMC Reference Flow 7.0, as well as of the Cadence Low Power flow.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Encounter, and VoltageStorm, are registered trademarks, and the Cadence logo is a trademark, of Cadence Design Systems, Inc.