Sequence Design Improves Clock Power, Performance of PowerTheater 65

Sequence Design announced PowerTheater 65, its flagship product for RTL power estimation and management, includes enhanced clock power estimation and reduction, as well as improvements to stimulus generation and performance. Clocks often consume 30% to more than 50% of the total power consumed by the chip. To manage these effects, PowerTheater 65 now provides designers with significant insights into where and how clock power is being dissipated. Making PowerTheater 65 more “silicon-aware,” the company has improved the tool’s clock gating, clock tracing, and clock power reporting capabilities.

PowerTheater 65′s hierarchical clock gating provides users with added control on where the integrated clock gating cells are to be inferred. This applies to both common clocks and enable signals that are shared across hierarchical boundaries. Additional report information gives users a clear picture of the number of registers gated.

PowerTheater 65 now incorporates major enhancements to clock tracing for gate-level designs as well. Fundamental clock tracing algorithms have been extended, tracing clock distribution networks with higher accuracy and automation, using combinational and sequential timing arcs in the timing libraries to guide clock tracing. Reports for clock domain tracing record the power of all elements traced in the clock domain.

Clock gating is a well-known technique to reduce power in clock networks. However, the quality of the reduction obtained is controlled by the design of the clock-gating enable signals. If the clock is enabled when data is not changing, the user is wasting power due to these unused clock toggles. A new clock enable condition power linter helps determine the effectiveness of the clock enables in a design by analyzing the relationship between the clock enable signal, clock signal and data signal for inferred registers in the design.

On the software and stimulus side, PowerTheater 65 enhances designer productivity by improving processing times to handle simulation data in the FSDB format. The new FSDB interface in PowerTheater 65 is almost 10 times faster and consumes half the memory of its predecessor. Gate-level simulations provide the most accurate power numbers, yet are time-consuming to run. In this release, PowerTheater 65 has been extended to support gate-level vectorless power estimation, complementing the tool’s ability to perform RTL vectorless power estimation. This allows designers to get early power estimates at both RTL and gate level, with and without stimulus. A final enhancement is PowerTheater 65′s ability to read encrypted Liberty (synlib) format libraries.

The latest PowerTheater 65 release is available now. North America list price begins at $175,000 for a 3-year TBL.

About Sequence
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence’s power and signal- integrity software solutions give customers the competitive advantage necessary to excel in aggressive technology markets, despite the demanding complexity and time-to-market issues of nanometer design. Sequence serves over 150 customers worldwide, in application segments such as consumer, wireless, mobile computing, multimedia, cell phones, digital cameras, network-on-chip processors, and other power-sensitive markets. Sequence has worldwide development and field-service operations and is privately held.