Altera Corporation (NASDAQ:ALTR) today introduced Quartus(R) II software version 6.1, offering designers superior levels of performance and productivity. The enhanced PowerPlay power optimization tool included in this version was designed in concert with the Programmable Power Technology in Altera(R) Stratix(R) III FPGAs, resulting in total power consumption savings of 50 percent compared to Stratix II FPGAs.
Quartus II software version 6.1 also delivers an average performance advantage of a full speed grade, as well as an average of 55 percent faster compile times for Stratix III FPGAs when compared to competing 65-nm devices.
“At 65 nm, optimizing power, performance and productivity is vital, placing an increasing importance on design software to deliver a satisfying design experience,” said Jordan Plofsky, Altera’s senior vice president of marketing. “Quartus II software version 6.1 and Stratix III FPGAs were designed and developed in careful collaboration so that our customers can design their next-generation systems with confidence.”
Stratix III FPGA Support With Enhanced PowerPlay Technology
This version of the PowerPlay power optimization tool is tightly linked with the Programmable Power Technology in Stratix III silicon, delivering a unique innovation that enables designers to achieve high performance and substantial power reductions—automatically and simultaneously. For designs targeting Stratix III FPGAs, the PowerPlay tool automatically analyzes a customer’s design during the compilation process to identify performance critical paths. It then sets the appropriate blocks to high-performance mode, while all other logic is set to low-power mode.
Performance and Compilation Advantages
Thanks to substantial advances in Altera’s core place-and-route technology, the combination of Quartus II software version 6.1 and Stratix III FPGAs delivers significant productivity advantages in both design performance and compilation speed, when compared with competing 65-nm FPGAs and their design software. Using the Altera performance benchmarking methodology (see white paper at www.altera.com/literature/wp/wpfpgapbm.pdf), Quartus II software version 6.1 and Stratix III FPGAs show a performance advantage averaging one speed grade, and up to three speed grades, when using the best-effort comparison method, and a compile time advantage averaging 55 percent, and up to 80 percent, when using the timing-constrained comparison method. Furthermore, Quartus II software requires approximately 50 percent less computer memory across both of these benchmark tests.
Reach Timing Closure Faster With Expanded TimeQuest Timing Analyzer Support
First introduced in Quartus II software version 6.0, the TimeQuest timing analyzer is the first and only timing analyzer from an FPGA vendor to offer comprehensive native support for the Synopsys Design Constraints (SDC) timing format, a proven industry standard for advanced and high-density designs. The TimeQuest tool enables designers to create, manage and analyze SDC timing constraints to reach timing closure quickly. This ASIC-strength timing analyzer has been enhanced in version 6.1 and now delivers more precise modeling for higher performance in Stratix III FPGAs, reduced compile times, easier constraint creation with the new SDC editor, easier board-level design with the data sheet generator and expanded support of the SDC format.
Quartus II Software Version 6.1 Features and Enhancements
Quartus II software version 6.1 includes software support for Altera’s new Stratix III devices as well as its other CPLD, FPGA and structured ASIC families. Additional highlights of the performance and productivity enhancements include:
- Multiprocessor support: Allowing parallel processing during compilation for computers with multiple processors results in a reduction in compile times. Quartus II software offers the first multiprocessor support from an FPGA vendor to take advantage of the new multiple-core processors.
- Detachable windows support: Quartus II software GUI users can now move various tool windows independently around their desktop, allowing easier design analysis and management.
- Chip Planner: A new integrated floorplanner and chip editor provides detailed design floorplan analysis and engineering change order (ECO)-editing capability.
- Advanced I/O timing: Allowing designers to enter board trace parameters in Quartus II software results in more accurate I/O analysis and faster timing closure.
- Pin planning enhancements: Automatic creation of a top-level design file from the pin planner results in more thorough I/O analysis and accelerated board design.
- Windows 64-bit version: Quartus II software 64-bit version running on Microsoft Windows XP Professional x64 allows designers to take advantage of computers with more than 4 Gbytes of memory.
- Expanded Linux support: Quartus II softwareincludes SUSE Linux Enterprise 9 support in addition to Red Hat Enterprise Linux.
Pricing and Availability
Quartus II subscription software version 6.1 is now available through local Altera sales representatives and distributors. Both the subscription edition and the web edition of Quartus II software version 6.1 will be available for download on December 4 at www.altera.com/download. Active Altera software subscribers will also receive a shipment of the Quartus II software beginning in December, as part of their subscription update.
Altera’s software subscription program simplifies the process of obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim(R) Altera edition and a full license to the IP Base Suite—ten of Altera’s most popular intellectual property (DSP and memory cores). The annual software subscription is $2,000 for a node-locked PC license. Quartus II design software supports major operating systems, including Microsoft Windows XP Professional x64, Microsoft Windows XP, Microsoft Windows 2000, Sun Solaris 8 and 9, Red Hat Linux Enterprise 3.0 and 4.0, and SUSE Linux Enterprise 9.
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