Aldec Offers SVET Support for Altera's Stratix III FPGAs

Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, including the renowned Active-HDL suite of tools, announced today System Verification Environment (SVET) support for Altera Corporation’s (NASDAQ:ALTR) new high-end Stratix III FPGA device family.

SVE supports all aspects of system-level design, developmentand verification. It includes an industry-leading common kernel HDL simulator, a set of on-line debuggers, code coverage, cross-probing tools and an industry-first, integrated simulator server farm manager (SFM) for automatic verification of ultra-large system-level designs.

“Aldec and Altera engineering teams are working together to ensure Aldec’s verification solutions are validated for Stratix III device support. The integration of Altera’s Quartus II design environment to Aldec’s mixed-language verification solutions provides customers with a seamless migration path for validating Stratix III designs,” stated Dr. Stanley M. Hyduke, CEO of Aldec, Inc. “The relationship between our companies continues to grow and we look forward to supporting our mutual customers on the next generation of Stratix designs.”

“Engineers designing with Stratix III devices have a broad range of system-level requirements, including intellectual property integration and multi-language support. In addition to meeting these requirements, Stratix III devices can accommodate multiple processors, memories and peripheral devices,” said Danny Biran, vice president of product and corporate marketing at Altera. “Engineers can then use the Aldec SVE solution to accelerate the verification cycle for their Stratix III designs.”

To speed verification and debugging of Stratix III designs, SVE can also handle OVA, PSL and SVA (System Verilog) assertion languages. Language templates and predefined test suites ease testing requirements for system-level designs.

Regression Automation
The newest trend in design automation is the use of code-coverage-driven intelligent test benches. However, such test benches require a considerably larger number of simulators than the traditional test benches. To handle a large number of test vectors and simulation results, Aldec has developed a server farm manager for Stratix III FPGAs capable of handling thousands of simulators in a highly efficient manner over corporate networks.

The SFM performs numerous operations and functions on design files such as running complex flows on multiple machines, storing, managing and comparing verification results, providing error reports and statistical summaries, optimizing license utilization, automatic network reconfiguration in case of failed nodes, and optimizing the usage of corporate computer power. The SFM option runs on 64-bit Linux simulation server farms and handles mixed designs and test benches written in VHDL, Verilog, SystemVerilog and SystemC.

“We place special attention to handling large designs in the most economical way to meet the needs of designers using Stratix III devices. This is why we developed full automation of the design verification process based on a powerful simulation server farm manager,” commented Dr. Hyduke.

Legacy Design Support
SVE co-simulates EDIF netlist blocks with HDL RTL blocks that allow use of legacy modules with Stratix III devices. Such capability is unique to Aldec’s common kernel HDL verification environment and allows unlimited switching of legacy FPGA designs to the newest silicon from Altera.

SVE will be available in January 2007, and will incorporate system-level verification products to facilitate validation of high-end Stratix III devices.

About Aldec
Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs.

Active-HDL and SVE are a trademarks of Aldec, Inc.