Sequence, Synfora Optimize SoC Power and Architecture
Sequence Design and Synfora Inc. today announced the creation of an integrated flow incorporating Sequence’s PowerTheater RTL power-analysis tool with Synfora’s PICO Express Application Engine Synthesis (AES). Strengthening the collaboration, Synfora has joined the InSequence Technology Partner Program, promoting EDA interoperability and advanced design methodologies.
“Our work through the InSequence program allows us to combine two powerful design technologies and offer our mutual customers the ability to explore power optimization at the architecture level,” said Simon Napper, Synfora president and CEO. “This combination provides the user with unequaled insight into performance, area, and power for advanced SoCs early in the design, when analysis and design tradeoffs can have maximum impact.”
PICO Express bridges the SoC design productivity gap by enabling the automatic generation of optimal architectures and synthesizable RTL from untimed C algorithms. As a result of using PICO Express, designers achieve significant reductions in the cost and risk of designing a SoC while being able to innovate and differentiate their end product. By integrating PICO Express with Sequence’s PowerTheater, users can now generate multiple trial implementations and then run PowerTheater to estimate power at RTL and, later, at the gate level. The generated power data allows users to examine tradeoffs for performance, area, and power to reduce design iterations and optimize the design’s power profile.
The integrated flow is now available; interested parties may contact either Sequence or Synfora for additional information.
Synfora is the latest in a series of InSequence partnerships, joining a variety of EDA vendors, foundries, IP providers, design services, platform vendors and universities.
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