Cadence Design Systems, Inc. (NASDAQ: CDNS) announced that Freescale Semiconductor, Inc. (NYSE:FSL, FSL.B) is continuing its successful migration to Cadence(R) Encounter(R) Test to improve the testability and manufacturability of its nanometer products. This move reflects the close relationship between the two companies at all levels as Freescale builds upon its long-term commitment to streamline design technology operations and establish common tools and methodologies based primarily on Cadence platforms for its broad line of semiconductor applications.
The migration plan remains on schedule and the first product employing Encounter Test is now in manufacturing.
“Based on results delivered and strong product support, Freescale is pursuing its transition to Cadence Encounter Test technology to realize the full benefits of higher product quality and lower test cost,” said Chekib Akrout, vice president of Design Technology at Freescale.
The Encounter technologies deployed at Freescale include True-Time Delay Test, which detects subtle delay defects while maximizing test coverage, and Encounter Test’s multiple architecture on-chip compression, which significantly reduces the cost of testing. As part of a broad effort to collaborate on innovative solutions for the next generation of design and manufacturing challenges, Freescale is a Cadence partner helping to drive new Encounter Test product enhancements.
Cadence Encounter Test, a key component of the Cadence Encounter digital IC design platform, delivers the industry’s most advanced test solution from RTL to silicon. Key technologies include both MISR and XOR compression architectures to lower cost of test, True-Time Delay Test to detect small delay defects and enable highest quality of shippable silicon, and Encounter Diagnostics, which identifies critical design-related issues by analyzing failure data from automated test systems to identify sources of yield loss.
“We are extremely pleased at the initial success with Freescale’s migration to Encounter Test made possible through our close relationship,” said Sanjiv Taneja, vice president of R&D for Encounter Test at Cadence. “Our long-term partnership and mutual commitment positions us very strongly to address Freescale’s testability and yield-ramp challenges in advanced process nodes.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence and Encounter are registered trademarks and the Cadence logois a trademark of Cadence Design Systems, Inc.