Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today introduced the Cadence(R) Logic Design Team Solution, which allows concurrent RTL design, enabling schedule predictability. This unique solution equips logic design teams with the elements they need – from verification and power to test and physical – plus plan-to-closure management and logical signoff in an integrated and holistic approach. It represents another deliverable in Cadence’s overall segmentation strategy, offering tailored solutions for specific types of engineering teams.
Logic design teams are asked to create increasingly sophisticated products in shrinking geometries while meeting a growing range of design objectives, such as correct reusable functionality, power efficiency, functional quality, adequate testability, and physical feasibility among others. As design complexity has increased, the interdependency of these objectives has grown as well, limiting the scalability of today’s manual, sequential and highly iterative approaches. The result is a growing scheduling ‘predictability crisis’, in which changes made to improve one goal degrade the others, increasing project risks and schedule convergence challenges.
“Time-to-market pressure combined with growing design complexity offers up many challenges,” said Jerry Alston, senior vice president at QLogic Corporation. “The combination of proven integrated front-end verification and implementation technologies for logic-design teams with a seamless linkage to system emulation enables us to stay ahead of the complexity curve. Our project teams clearly have an advantage taking this combination of front-end and systems approach, reduced overall product risk, and improved execution from architectural plan to logic design and verification to system-level closure.”
The Cadence Logic Design Team Solution integrates technology from the Cadence Incisive(R) functional verification and Encounter(R) digital IC design platforms. It integrates design, early verification and front-end implementation tasks into a set of objective-focused sub-flows, and automates the concurrent management of the design’s progress toward these objectives. The solution takes a concurrent ‘Design with’ approach – with early considerations for interdependencies and iterative flow aspects – as opposed to serial and highly iterative design. The architecture includes four major elements and an overall plan-to-closure management and logical sign-off solution, while leveraging industry-standard formats such as SystemVerilog. The Logic Design Team Solution includes:
- Design with Verification – early design verification including assertion-based formal analysis, simulation and acceleration, and verification management
- Design with Power – integrated low-power design and verification management across the front-end flow
- Design with Physical – reduces logic-physical iterations by providing accurate estimates of timing using physical engines from implementation within the logic-design environment
- Design with Test – integrates test with the logic-design environment to develop and debug high-quality test infrastructure with minimal iterations
- Design Logical Signoff – comprehensive implementation handoff checks and analysis to verify front-end closure with predictability and confidence
- Design Management – brings unparalleled predictability from plan to closure through an automated plan and metrics-driven management solution which tracks progress of the evolving design against all its functional, performance, and schedule objectives
“At Kawasaki Microelectronics, we rely on Encounter Test technology for the creation and production of deep submicron devices indispensable for the low-power consumer and high-performance information technology markets we serve,” said Yoshito Muraishi, director of CAD development at Kawasaki Microelectronics, Inc. “We are very pleased with the results of the Cadence Logic Design Team Solution, and with its Design with Test aspects. The deep level of integration and synergies between testability and synthesis, verification, timing analysis will further accelerate our time-to-market, reduce design iterations, improve shipped product quality and accelerate yield ramp.”
“The schedule predictability crisis is real,” said Ted Vucurevich, senior vice president and chief technology officer at Cadence. “We have been aggressively extending front-end technology and methodology innovation, building user-centric integrated flows and solutions across design and verification. The Cadence Logic Design Team Solution brings a practical and holistic approach to achieving predictability with an automated concurrent design process, replacing the ad-hoc serial, fragmented and manual approaches of the past.”
The Design-for-Test element will be featured at the International Test Conference in San Jose on October 24, 2006. Elements of the Cadence Logic Design Team Solution are described in more detail in the front-end design white paper.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, the Cadence logo, Encounter and Incisive are registered trademarks of Cadence Design Systems in the United States and other countries.