Cadence, SMIC Create 90nm Low-Power Digital Reference Flow

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Semiconductor Manufacturing International Corporation (SMIC) (NYSE: SMI; SEHK: 0981.HK) today announced the companies have jointly developed the low-power digital reference flow to support SMIC’s advanced 90-nanometer process technology. The reference flow, which includes support for the Cadence(R) Encounter(R) Timing System, is now available to address the increasing needs of designers developing ICs for the computing, consumer, networking and wireless markets.

The reference flow incorporates the Cadence Encounter digital IC design platform and Cadence Design for Manufacturing (DFM) technologies to address nanometer design challenges such as low power, complex hierarchical designs, timing and signal integrity (SI) signoff. The reference flow was developed using SMIC’s 90-nanometer process technology and validated with sample designs. Cadence is one of the first electronic design automation companies to launch a 90-nanometer RTL-to-GDSII reference flow with SMIC. New Cadence technologies, such as the Encounter Timing System, were incorporated into this flow for static timing analysis (STA) signoff.

“Our collaboration with Cadence helps to drive our goal of continuing to enable the Chinese as well as global semiconductor market,” said Paul Ouyang, vice president of Design Services at SMIC. “As a leader in complex, low-power and digital design solutions, Cadence has provided its unique technology and expertise to create this reference flow. The 90-nanometer SMIC low-power reference flow, fueled by Encounter Timing System and other advanced digital IC design technologies from Cadence, along with SMIC’s process technologies, will ensure high levels of quality and productivity for our customers, and offers a faster, validated, reduced-risk path to silicon.”

The SMIC-Cadence Reference Flow is a complete RTL-to-GDSII, low-power flow focused on efficient energy utilization for 90-nanometer system-on-chip (SoCs). It consists of power awareness throughout all necessary design steps, including logic synthesis, simulation, design for test, equivalence checking, silicon virtual prototyping, physical implementation and complete signoff analysis. The Encounter low-power flow is one of the industry’s first complete low-power solutions for modern energy-efficient SoCs. The design, implementation and verification technologies are completely integrated to provide the designers with a big productivity boost. This reference flow deploys the Cadence Encounter wires-first continuous-convergence methodology and allows designers to quickly generate a feasible netlist and virtual prototype to identify and optimize power, timing, SI and routing early in the design cycle.

In addition, this flow provides a comprehensive platform for designers to drive RTL-to-GDSII with emphasis on fast, accurate and automatic timing, power and SI closure. It addresses hierarchical block partitioning, physical timing optimization, 3-D RC extraction, IR drop, leakage and dynamic power optimization, crosstalk glitch and delay analysis. This flow enables designers to architect and optimize advanced designs in a systematic, predictable way, providing the highest quality of silicon.

“We are pleased to collaborate with SMIC and launch this reference flow based on its 90-nanometer process technology,” said Mike McAweeney, vice president of business development of Industry Alliances at Cadence. “Our engagement with SMIC puts in place another vital link in our customers’ design chain, ensuring a manufacturing aware design chain from idea to silicon. It also highlights the growing number of foundries and design houses in China that rely on the Cadence digital IC design flow.”

The SMIC-Cadence low-power digital reference flow offers a starting point to create energy-efficient, sub-130 nanometer SoCs. The flow incorporates several innovative Cadence technologies, including power-aware design flow, Encounter Timing System, Encounter RTL Compiler global synthesis, SoC Encounter RTL-to-GDSII system, Cadence extraction technology, VoltageStorm(R) power analysis with PowerMeter functionality, and CeltIC(R) Nanometer Delay Calculator (NDC), using the highly accurate effective current source delay model (ECSM) to reduce time-to-volume for low-power consumer applications.

The SMIC and Cadence low-power digital reference flow kit is available to SMIC customers. SMIC customers may request the reference flow by contacting SMIC’s Design Services or please contact your SMIC account manager.

About SMIC
SMIC (NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) manufacturing service at 0.35-mm to 90-nm and finer line technologies. Headquartered in Shanghai, China, SMIC operates three 200-mm fabs in Shanghai and one in Tianjin, and one 300-mm fab in Beijing, the first of its kind in Mainland China. SMIC has customer service and marketing offices in the U.S., Italy, and Japan as well as a representative office in Hong Kong.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Cadence, the Cadence logo, CeltIC, Encounter, and VoltageStorm are registered trademarks and Encounter is a trademark of Cadence Design Systems, Inc.