IP/SOC Conference for IP-based SoC Design

IP/SOC 2006 (IP-based SoC Design) will be the 15th edition of the working conference on hot topics in the design world, focusing for the past 6 years on IP-based SoC design and held in the well known Silicon and Alliance Nanometer Valley in the French Alps.

The areas of interest for the IP/SOC 2006 event include (but are not restricted to):

  • Silicon and Software IP design and packaging
  • IP and system configurability
  • Impact of Nano technology
  • IP /SOC design flow; Architectural exploration and performance analysis
  • IP based design Platform (Asic, Structured ASIC ,FPGA )
  • IP/SoC qualification, emulation and prototyping
  • ESL, Transaction level modeling for IP based SoC design
  • Reuse practice and design for reuse
  • Reuse standard or pre standard
  • Collaborative IP Based Design

Similar to the previous events, this working conference will be partitioned into technical papers, panels and invited papers, with a balanced contribution from industrial and academic participants.

Confirmed keynote talks

  • “Investment opportunities in IP” by Jacques Benkoski (US Venture Partners)
  • “IP market analysis” by Jim Tully (Gartner / Dataquest)

A full track of technical panels addressing the most challenging topics will be animated by the best worldwide specialists in the field:

  • “Design Knowledge sharing or IP reuse: Is design reuse practical and viable in an enterprise ?” chaired by Richard Wallace (EETimes) with the tentative participation of Alcatel, D&R, Thalès Group, Cisco Systems , Mentor, Cadence, etc
  • “Automated SoC Assembly-dream or reality ? There are solutions to the pain of integration” moderated by Jim Tully (Gatner/Dataquest) with the participation of Arm , Synopsys, Open–Silicon, etc
  • “How Disruptive Technologies will Shape SoC Design and EDA Tool Development” with the participation of IBM, Synopsys, Silistix, etc
  • “How to evaluate and choose hard IPs” moderated by Jim Lipman with the participation of Mosaid, Freescale, Impinj, ARM and Virage Logic
  • “Network on chip” moderated by Huy Nam Nguyen (Bull) with the participation of Arteris, STMicroelectronics, University of Paris, Silistix
  • “Integrating Nonvolatile Memory in SoC Designs: Save Time and Reduce Design Costs” with the participation of Innovative Silicon, Kilopass, eMemory

A special Spirit panel organized by Chris Lennard (ARM) and moderated by Pierre Bricaud (Synopsys) will present the state of the art on Design flow integration with IP-XACT from The SPIRIT Consortium: from proof point to industrial adoption.

Training and seminars will be hold ahead of the conference and after the conference (see below).

Each year IP/SoC Conference proud to recognize the excellent, novel, innovative and highly practical design ideas that authors contribute. Excellence in design – whether it be within an IP block or a complete system continue to be the future of the IP/SoC industry. This year, in conjunction with sponsors CEA/LETI and the LSI IP Design Award Committee in Japan, it will offer two prizes to the most interesting and innovative design papers.

Papers will be judged on both the originality and practicality of the design, and the quality and presentation of the paper. Finalists will be able to take part in a poster session in the main exhibition area during the lunch and afternoon coffee break of the first day so that conference delegates can mingle and discuss the designs with the authors. Voting by delegates and judges shall take place during the first day and the two winners shall be given their awards during the prestigious conference banquet on the evening of the first day.

In addition to the IP/SoC 2006 working conference, the attached exhibition gives you the opportunity to see the reality of a SoC connected world. The exhibition will allow you to meet the most advanced suppliers and see the latest products.

Book your space now.

You can submit an electronic version of your extended abstract (3 pages minimum) in a Word, PDF or PostScript format using one of the following methods:

1. By using the Online Submission Form (## RECOMMENDED ##)
2. By sending an e-mail containing the paper title, your names, the name of the contact author, postal and e-mail address, telephone and fax number, as specified in the online submission form.

All correspondence with authors will be handled by e-mail.


On December 5th

  • Nanometer MPSOC Design Using Configured Cores by Steve Leibson (Tensilica, Inc.)
  • The IP Exact 4.1 Specification form the Spirit consortium: Technical awareness training by Chris Lennard (ARM)
  • IP based Collaborative Design and Reuse by Gabrièle Saucier (D&R)

On December 8th the whole day

  • Training Course on Formal Verification by Huy Nam Nguyen from Meta Symbiose


  • Prof. K. ASADA – Tokyo University, Japan
  • A. BECKMANN – sci-worx GmbH, Germany
  • P. BRICAUD – Synopsys, France
  • T. DANIELS – LSI Logic, UK
  • B. DE LOORE – Philips Semiconductors, Netherlands
  • P. DWORSKY – Synopsys, USA
  • L. FLANAGIN – ARC International, USA
  • J. HAASE – EDAcentrum, Germany
  • F. KLEITZ – Alcatel, France
  • H. KRUPNOVA – STMicroelectronics, France
  • P. MAGARSHACK – STMicroelectronics, France
  • B. MARTIN – Mentor Graphics, USA
  • S. MORI – IPTC, Japan
  • H.N. NGUYEN – Bull, France
  • K. REID – Cadence, UK
  • Prof. W. ROSENSTIEL – FZI Karlsruhe University, Germany
  • H. SANGHA – LSI Logic, USA
  • G. SAUCIER – Design And Reuse, France
  • D. VELLOU – CEA/LETI, France
  • Prof. N. WEHN – University of Kaiserslautern, Germany


  • Deadline for submission of the extended abstract: September 25, 2006
  • Notification of acceptance: October 23, 2006
  • Final Version of the manuscript: November 13, 2006
  • Working Conference: December 6-7, 2006

Espace Congres du World Trade Center
5 place Robert Schuman
38 000 Grenoble