Cadence Design Systems, Inc. (NASDAQ: CDNS) today further extended the capabilities of the Cadence(R) Encounter(R) digital IC design platform with the announcement of its Encounter Timing System. This new system provides customers a single source and consistent view of timing, signal integrity and power — from design and physical implementation, through final signoff analysis. In addition to addressing the needs for implementation and signoff analysis, front-end design teams will also benefit from its global timing debug features for accurate root-cause analysis and fast timing closure, which is driven by a powerful graphical user interface.
With Encounter Timing System, digital IC designers working through the challenges of continually shrinking process nodes gain improved time to market, better productivity, the ability to bring signoff-quality timing and signal-integrity analysis to all aspects of the design flow, and total cost of ownership.
The Cadence Encounter Timing System brings with it all the strengths of CeltIC(R) NDC’s leading signal-integrity (SI) analysis and pessimism removal together with signoff quality timing, delay calculation, power integrity, and tight links to Encounter Conformal technologies for a holistic and system-level view of timing through all stages of the design flow. Other features include critical path simulation, SPICE tracing, electro-migration analysis, statistical timing, and the ability to account for power-optimization and low-power design constructs.
To simplify the designer’s job of identifying and pinpointing the source of timing problems, the Encounter Timing System includes powerful graphic-based timing-debug features for accurate root-cause analysis and fast timing closure. The Encounter Timing System also supports 3rd-party formats, such as Liberty and SDCs, while harnessing the full power of the effective current source model (ECSM), the industry’s first and only open and production-proven format for advanced delay modeling. The result is unprecedented usability, predictability and correlation for implementation and analysis, and compatibility to common industry design flows for ease of adoption.
“We worked with Cadence to validate the Encounter Timing System’s signal integrity, static and statistical-timing-analysis features in conjunction with our 65-nanometer-based TSMC Reference Flow 7.0,” said Ed Wan, senior director of design service marketing at TSMC (TSE: 2330, NYSE: TSM). “Designers now have access to advanced timing that provides consistency through the design flow and accounts for the interdependencies of timing, signal integrity and power.”
“We’ve depended on the Encounter timing engine for timing optimization and final signoff for our most advanced designs,” said Tim Conners, design engineer at Atheros Communications (NASDAQ: ATHR). “Encounter Timing System is a natural extension for our implementation and signoff flow, and its performance, consistent accuracy through the flow, and superior usability for both timing and signal integrity signoff has made our decision to standardize on it very simple.”
“We conducted several rigorous benchmarks and found Encounter Timing System achieved top accuracy, performance and capacity on our multi-million gate designs,” said Eka Laiman, Design Manager at Magnum Semiconductor. “We are very happy with Encounter Timing System’s ease-of-use and also the excellent applications engineering support and fast turnaround for our enhancements. Encounter Timing Systems fits very well with our Cadence front-end design flow speeding up time-to-market on our high-volume digital video recorder chips.”
As customers make the transition from 90- to 45-nanometer design methodologies, having a homogenous view of timing for both implementation and signoff is not a luxury, it is a categorical imperative. Timing closure in the presence of electrical effects, silicon variability, and design susceptibility to failure at these technology nodes and beyond will demand unprecedented levels of intelligence from both design tools and the expertise required to achieve it. Managing this complexity algorithmically and holistically is only part of the challenge. Providing timing-debug tools to allow digital IC designers to quickly and intuitively identify the precise source of a timing issue in a sea of infinite possibilities is another thing altogether. Any viable timing solution will need to address both.
“The Cadence Encounter digital IC design platform is the integrated RTL design and implementation flow for complex and low-power designs at 90 nanometers and below,” said Wei-Jin Dai, corporate vice president of R&D at Cadence. “The Encounter Timing System extends our lead in signal-integrity digital-IC-design solutions to signoff timing and is a direct result of the resources Cadence continues to invest into advanced technology development.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, the Cadence logo, Encounter and CeltIC are registered of Cadence Design Systems, Inc.