Jasper Design Automation, provider of breakthrough high-level formal verification solutions, today announced immediate availability of GamePlan(TM) Verification Planner, an intuitive, free downloadable tool that generates and tracks the progress of verification plans. This first-of-its-kind tool promotes easy collaboration between verification team members through a single, comprehensive structured environment that identifies the design features that need to be tested and the verification technologies required for testing. GamePlan Verification Planner provides a much needed solution for systematic verification, enabling vital prioritization and progress tracking for each feature tested, while also driving higher quality, shorter schedules and greater predictability.
“We are making GamePlan’s technology available for free in order to facilitate the easy capture and tracking of systematic verification plans that make the most of formal, simulation and other verification methods,” stated Craig Cochran, vice president of marketing at Jasper. “Companies that take a systematic approach to verification planning are the most successful at integrating formal with simulation, and at building a highly productive verification environment. Ultimately, Jasper is enabling companies to ensure correctness where it matters most by providing a means for the successful adoption and integration of formal within existing verification flows.”
With the intention of fostering a community around this free offering, Jasper has created an online micro-site for GamePlan. This site provides free downloads of software and documentation, as well as access to user forums, and areas for sharing ideas and verification test plan examples.
GamePlan Verification Planner is currently available for free download from the Jasper GamePlan micro-site.
About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company delivering full-formal IC verification as a competitive advantage for its customers. Flagship product, JasperGold(R) Verification System, is the first to deliver complete “deep formal” systematic verification, ensuring correctness where it matters most. Without needing any testbench development, JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for all usage modes. Jasper’s formal ABV solution, JasperGold(R) Express, provides the industry’s leading “light formal” solution. It complements simulation-based approaches by accelerating bug hunting and elimination, as well as coverage attainment. The JasperGold family automatically isolates bugs with a fast, unique debugging capability. By isolating bugs earlier than simulation or formal-assisted simulation tools, and then proving the absence of bugs, JasperGold trims crucial months off design schedules.
Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner and GamePlan are trademarks or registered trademarks of Jasper Design Automation, Inc.