Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba has adopted Cadence(R) QRC Extraction for its most advanced 65-nanometer design flows. Cadence QRC Extraction provides silicon-accurate parasitic extraction for next-generation process nodes, including sensitivity-based and chemical-mechanical polishing (CMP) model-based extraction.
“To address our design and methodology requirements at 65 nanometers and beyond, we require a solution that can deliver exceptional accuracy and includes advanced statistical and silicon variation modeling,” said Takashi Yoshimori, technology executive, SoC-Design of Toshiba’s Semiconductor Company. “After an extensive evaluation process, we found that Cadence QRC Extraction meets our requirements for 65-nanometer accuracy today, and we have confidence that it will continue to meet our requirements for 65 and 45 nanometers, giving us the ability to move into lower and lower geometries.”
Cadence QRC Extraction provides manufacturing-aware silicon accuracy over other extraction technologies for cell-based digital designs. It dramatically reduces processing time with its near-linear performance scalability across multiple network CPUs and compute farms. It also delivers robust multi-corner support and native incremental signoff extraction to the Cadence Encounter(R) digital IC platform.
“Toshiba’s adoption of Cadence QRC Extraction is a strong endorsement of our leading extraction technology and its ability to manage the highest levels of process and design complexity,” said Dr. Marc Levitt, vice president, Design for Manufacturing, at Cadence. “We look forward to working closely with Toshiba as they continue to deploy the full benefits of Cadence QRC Extraction in developing their most advanced 65- and 45-nanometer designs and methodologies.”
The Cadence product segmentation strategy provides customers with multiple levels of technology tailored to specific levels of design complexity. Cadence QRC Extraction is available in L, XL and GXL offerings.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.