DVCon: Call for Paper, Panel and Tutorial Proposals
The 2007 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions. Proposals that reflect real experiences using hardware design and verification languages, advanced tools and methodologies are encouraged.
DVCon 2007 will be held February 21-23 at the DoubleTree Hotel in San Jose, California. It is the premier conference focusing on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The conference will focus on the use of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA, as well as general purpose languages such as C and C++.
All paper, tutorial and panel submissions related to using HDLs, HVLs or other languages used for hardware design or verification will be considered. All topics can be found online.
Paper and panel proposals are due September 19, 2006
To submit a panel proposal, please email Kathy Embler at MP Associates. Paper proposals must be submitted online. Submission site opens on September 1, 2006.
Proposals are also being accepted for special sessions and sponsored tutorials. Special sessions may consist of embedded tutorials of one to two hours in length or may be focused on a specific topic with a list of invited papers/presentations relevant to that topic. Special session tutorials proposals must be submitted via email to Kathy Embler.
Sponsored tutorials are due October 5, 2006
A limited number of sponsored tutorials will be also available. Proposals are due October 5. To submit sponsored tutorial ideas, please contact Kathy Embler at MP Associates.
Accellera sponsors DVCon. Accellera is an industry consortium dedicated to the development and standardization of EDA languages, methods and formats, including design and verification languages.
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