French fabless semiconductor startup, MnD Semiconductors, has developed a chip architecture that can be easily scaled from low cost, high definition, video decoders to high performance, real time, multi-channel, video encoders and transcoders. Called Silver Screen(TM), it will be launched at the IBC2006 show in Amsterdam from 8-12 September on Stand 7.925.
MnD is now looking to turn this architecture into a family of chips with the primary focus being on high definition (HD) encoding, transcoding and decoding solutions for mobiles. The increasing integration of camcorders into mobile phones means that manufacturers need to be able to encode HD video, transcode it to MPEG4 AVC/H.264 to minimise storage space and then play it back at HD 1080p resolution on HDTVs. MnD’s Silver Screen(TM) HD video codecs provides an effective means to do all this at a fraction of the silicon cost and power consumption of existing solutions.
The architecture is fully scalable and based on an array of interconnected, fully programmable, 32-bit RISC processors, which are derived from the Sun SPARC architecture. “This multi-processor array approach with its user-configurable application software library is very different from the approach taken by other solution providers who use combination of FPGAs, general purpose processors, DSPs (Digital Signal Processors) and hardware accelerators,” says Ian Walsh, CEO of MnD. “It allows a range of devices to be statically developed or dynamically configured for different price and performance points, all running the same software, giving significant economies of scale and reducing the cost, risk and time for system developers,” he adds. The Silver Screen(TM) architecture is proven in FPGA implementation and some customers are already shipping full custom chips based on the underlying technology into very cost sensitive and competitive markets.
A required processing power can either be achieved by having a single processor working flat out or, as in Silver Screen(TM), by having an array of processor cores running at lower processing speeds that aggregate together to deliver the required processing. The cores in the array are very small and consume very little power, which even when all added together, provides a solution that is smaller, cheaper and less power hungry than a single high performance core solution with accelerators. Power consumption can be further reduced by switching off cores when not required.
The company’s Silver Screen(TM) library of user-configurable software for AVC video applications makes it simple for developers to use the chips by simply loading up the appropriate set of modules to meets the tasks required. The company has also developed a methodology for adding application specific instructions to the processor and programmable coprocessors in hardware to further accelerate math intensive algorithms. The architecture is being presented at the MPSOC’06 Forum in Colorado in mid August.
For HD video encoding, decoding and transcoding, a single multiprocessor chip can be implemented on a 65nm process cost effectively, in conjunction with fully tested software libraries. The chip can be used for decoding and displaying DVB-H video in a mobile phone, creating economies of scale and higher volumes.
Because it is based on an array, the MnD architecture will scale to handle encoding of multiple channels of video up to resolutions of 1080p at 50 frame/s, as well as transcoding. High performance real time encoder manufacturers could use the chip to replace the many expensive FPGA and DSPs that are currently used to implement the compression algorithms. One or more of the chips can be interconnected and cost effectively scale for more complex higher performance multichannel and professional broadcasting applications.
Transcoding is becoming important in CCTV and video surveillance systems where the bandwidth and operational cost advantages of AVC technology are required for network expansions and to convert current MPEG-2 feeds, maintaining the legacy infrastructures and investments. Being able to manage the multiple channels with low cost, fully programmable chips significantly cuts the cost, size and power required for a CCTV system.
The Silver Screen(TM) chip will also include an industry standard processor core for OEM use with an API to the HD codec array. It will also have a DDR interface for memory and an HDMI for displays.