Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of the industry’s only full rate SPI-4.2 solution based on a low cost FPGA fabric. This solution, consisting of a LatticeECP2(TM) FPGA plus a Lattice-developed soft Intellectual Property (IP) core, is fully compliant with the Optical Internetworking Forum’s (OIF) System Packet Interface Level 4 (SPI-4) Phase 2 Standard, a popular parallel interface found in telecom/datacom applications at 10Gbps rates and below. The ability to operate at the full 10Gbps line rate is made possible by Lattice’s unique sysI/O(TM) interface structure, which contains pre-engineered elements designed to support the implementation of very fast, source synchronous interfaces such as DDR2 and SPI-4.2. By delivering high-end FPGA features and performance in its low cost LatticeECP2 FPGA fabric, Lattice is able to provide the first FPGA-based SPI-4.2 interface requiring less than $5.00 of FPGA logic in production volumes.
Lattice’s SPI-4.2 solution is supported by Lattice’s new IPexpress(TM) FPGA design tool module. Included as a standard feature in Lattice’s ispLEVER(R) design tool suite, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer’s desktop. This allows users to customize Lattice’s extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.
“An FPGA-based SPI-4.2 solution provides system designers with a flexible way to support intelligent bridging functions interfacing with today’s high-performance communications ASSPs, including network processors, traffic managers, MACs or framers,” said Stan Kopec, Lattice corporate vice president of marketing. “Until now, designers could implement full rate SPI-4.2 bridges supporting complex packet flow and traffic management policies only on premium FPGA devices: low cost FPGAs could not support the I/O or logic speeds. This latest announcement vividly demonstrates Lattice’s corporate philosophy of “More of the Best,” combining the best 90nm FPGA silicon technology with the best FPGA architecture and features to deliver more performance at a more cost-effective price point.”
The new SPI-4.2 soft IP core requires fewer than 5000 FPGA look-up tables and therefore can be implemented along with other user logic in most LatticeECP2 family members, from the LatticeECP2-12 device through the largest member of the family, the LatticeECP2-70 device. The SPI-4.2 core operates at interface speeds of up to 750Mbps while fulfilling all requirements of the SPI-4.2 interface protocol, including support for up to 256 logic channels, calendars, transmit and receive status, programmable burst size and DIP4 error checking.
LatticeECP2 sysI/O Structure
The I/O cells in the LatticeECP2 FPGA devices contain a number of pre-engineered elements to allow the easy implementation of source synchronous interfaces. These elements include dedicated precision DQS/strobe delay control, dedicated double data rate (DDR) I/O registers (for muxing and demuxing data), automatic DQS to system clock domain transfer, gearbox logic to match the I/O speed with the FPGA fabric performance and low skew edge clocks. These elements can be easily configured in Lattice’s ispLEVER design tool to implement a variety of high-performance interfaces.
About the LatticeECP2 Family
The LatticeECP2 family, ranging in density from 6K to 70K look-up tables, is the second generation of the EConomy Plus FPGA concept. Developed on 90nm Fujitsu CMOS technology utilizing 300mm wafers, this device family cuts FPGA prices to under $0.50 per 1,000 look-up tables (LUTs) in high volume. Compared to Lattice’s first generation 130nm LatticeECP(TM) FPGAs, the new family also increases available logic density to 70K LUTs, increases the number of 18×18 multipliers to 88, boosts I/O performance over 50% and enhances configuration capabilities. Capabilities added for the first time to this class of FPGAs include pre-engineered 400Mbps DDR2 memory interface support, configuration bitstream encryption and dual-boot configuration support.
Pricing and Availability
Samples of the first members of the LatticeECP2 family are currently available. Individual family members are planned to move to production beginning in August with most device options production released by year-end. Prices for the various device options vary by device density, package and speed grade. In high volume, prices start below $.50 per thousand look-up tables.
Lattice’s SPI-4.2 soft IP core for the LatticeECP2 is available now. List price for the core is $15,000 for the netlist version. More information on Lattice IP and devices can be found on the Lattice website.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC(R)) and Programmable Digital Interconnect Devices (ispGDX(R)). Lattice also offers industry leading SERDES products. Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high performance, non-volatile and low cost FPGAs. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeECP, LatticeECP2, IPexpress, ispLEVER, ispPAC, ispGDX, sysI/O and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.