DoGav Systems, a leading provider of software and hardware consultancy specializing in Freescale Semiconductor’s PowerQUICC(TM) communications processors built on Power Architecture(TM) technology, today announced the availability of two new additions to its range of microcode products for PowerQUICC processors: System Fabric Plane protocol (SFP.1, Internal TDM), designed for Freescale’s MPC8280 PowerQUICC II, MPC83xx PowerQUICC II Pro, and MPC8555E/8560 PowerQUICC III processors, and Generic Framing Protocol (GFP), designed for Freescale’s PowerQUICC I, PowerQUICC II, PowerQUICC II Pro, and MPC8555E/8560 PowerQUICC III processors.
SFP.1, also sometimes referred to as Pseudo-Wire, is a multiplexed voice over packet protocol. Media processing, such as voice conferencing and voice mail, is being increasingly implemented using off-the-shelf host platforms. At low densities, VoIP works well for this, but when the density scales up, VoIP is no longer viable, as the processing overhead is too high. Even for some lower density host media processing applications, the latency of VoIP becomes an issue. SFT.1 is perfectly suited to connect high density host media processing platforms into a larger system.
In addition, as voice and data networks converge, TDM busses will migrate to packet bus implementations. However, this migration will not occur all at once, and existing telephony equipment will have to continue to inter-work with the newer packet bus equipment for some time. SFP.1 is perfectly positioned to enable this migration.
SFP.1 is also a perfect protocol for carrying many TDM voice/data calls over the packet bus itself.
The Generic Framing Protocol (GFP, ITU-T G.7041) provides a set of functions that support a generic interface to underlying frame representation systems (FRSs). The interface layer allows mapping of variable length, higher-layer client signals over a transport network like SDH/SONET. The client signals can be protocol data unit (PDU) oriented (like IP/PPP or Ethernet Media access control [MAC]) or can be block-code oriented (like fiber channel). Unlike the popular HDLC protocol, where the bandwidth expansion is non-deterministic, GFP uses only the information in its header for frame delineation, allowing deterministic bandwidth and reducing latency.
“The SFP.1 and GFP microcode modules are the latest additions to our growing list of microcode products, and a further illustration of our commitment to the development of microcode for Freescale’s PowerQUICC communications processors”, said David Gabbay, President and CEO of DoGav Systems. “We are very excited about these two products that were developed as a direct result of market demand and we are already in discussion with customers seeking to deploy them in their systems.”
“DoGav Systems’ advanced microcode implementations for PowerQUICC processors and QUICC Engine(TM) technology are valuable contributions to Freescale’s growing library of next-generation microcodes optimized for customer and market requirements,” said Jon Devlin, director of systems engineering for Freescale’s Digital Systems Division. “These highly efficient microcode implementations from DoGav Systems are designed to enhance the overall performance of a system, while providing a cost-effective, quickly deployable alternative to adding hardware to achieve new functionality in communications and networking applications.”
The PowerQUICC II processors and the MPC8555E/8560 PowerQUICC III processors incorporate two main components: an embedded core processor built on Power Architecture technology and a communications processor module (CPM) — a dedicated RISC engine optimized for handling communications tasks. The PowerQUICC II Pro processor family incorporates a next-generation communications engine known as QUICC Engine technology.
Both the CPM and QUICC Engine technology support a wide range of protocols, and they operate independently from the core processor. They have their own instruction set and can be programmed via “microcode” by a handful of companies carefully selected and licensed by Freescale. This presents the opportunity for implementing higher levels of networking protocols and/or introducing new protocols, resulting in considerable application complexity offload and an increase in the overall performance.
The first SFP.1 release is expected in August 2006 and will support 1 millisecond frame rate. A second release, supporting 125 microsecond frame rate, is expected in September 2006. Both releases will support all 256 MCC TDM channels, and will be available for the MPC8280 PowerQUICC II, the PowerQUICC II Pro, and the MPC8560 PowerQUICC III processors.
The PowerQUICC I GFP release is available with immediate effect. The PowerQUICC II and PowerQUICC III releases are expected in August 2006, and the PowerQUICC II Pro release is expected in September 2006.
About DoGav Systems
DoGav Systems is a leading provider of software and hardware consultancy and training services. It specializes in Freescale’s processors built on Power Architecture technology, in particular the PowerQUICC(TM) family of communication processors. It has a proven track record of over 20 years supporting Freescale customers in developing market-leading products for the communications equipment market. DoGav Systems is one of Freescale’s most experienced and active microcode developer. Since receiving its license in 2000, it has developed numerous customized microcode packages for both small and large Freescale customers. These packages are now successfully deployed in commercial products. In addition, DoGav Systems also offers more than 30 off-the-shelf microcode products for the PowerQUICC(TM) I, PowerQUICC(TM) II, PowerQUICC(TM) III and PowerQUICC(TM) II Pro processors.
DoGav Systems Ltd
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