Macraigor Systems LLC, a leading supplier of Joint Test Action Group (JTAG) and background debug mode (BDM) connection solutions for on-chip debugging, today announced the availability of J-SCAN Version 2.1, the newest release of its high-speed, low-cost boundary-scan debug and programming tool. This new technology allows circuit designers to facilitate early test development, thereby shortening the development cycle and prototyping process.
Version 2.1 of J-SCAN communicates to the target with a USB 2.0- and USB 1.1-compatible interface that runs in high speed or full speed modes. This gives a performance increase of more than 10X compared to the previous version of J-SCAN. Additionally, J-SCAN 2.1 has full support for serial peripheral interface (SPI) Flash programming, supporting those systems using field-programmable gate arrays (FPGAs) and other embedded devices.
J-SCAN provides significant advantages compared to logic analyzers and oscilloscope probes, permitting designers to observe the behavior of the pins under a ball grid array (BGA) device in real time on their PCs. The J-SCAN debug and programming tool also allows designers to manually place the pins to any logic state with a simple point-and-click of the mouse. Engineers can observe logic state transitions and instruction addresses sent and received across individual pins, providing an unprecedented level of visibility in debugging SOCs, integrated components and new board designs.
For the first time, the IC designer now has visibility into and control of every pin. If the CPU is not yet available and the designer needs to program flash memory, doing so simply involves setting up the signals (address, data, enables), selecting a data file and pressing the PROGRAM button. The included USB 2.0 download cable enables programming times of minutes, rather than hours or days. Utilities to program FPGAs and complex programmable logic devices (CPLDs) are also available.
“Because of cost and time-to-market pressures, hardware designers are faced with getting board and component designs right the first time,” said Craig Haller, chief engineer at Macraigor Systems LLC. “J-SCAN helps them achieve this goal by providing a quick, simple and effective way to debug circuits, perform non-destructive continuity testing and validate boundary-scan chain integrity independent of the their present design tools. The enhancements in J-SCAN 2.1 enable engineers to work with a broader range of designs and components and significantly increase debugging performance.”
J-SCAN works independently of any logic inside the JTAG device, so no special firmware, code or logic needs to be installed. The J-SCAN debug and programming tool is extremely easy to use, allowing designers to be up and running in minutes. The designer simply plugs in the Macraigor usb2Demon interface, drops any type of integrated circuit (IC) device on the screen and presses the scan button. Instantly, all activity on every boundary-scan enabled pin on any device or chain of devices is visible on the PC or laptop.
The J-SCAN manual is written in a tutorial style that provides users with not only the J-SCAN features and how to simulate faults, but also the fundamentals of boundary scan. No prior boundary-scan experience is required. Multiple J-SCAN video tutorials featuring a fully populated demonstration board are available online as well.
Pricing & Availability
Available for order now, J-SCAN is priced at $1,895 USD. The kit includes the J-SCAN debug and programming software, USB 2.0 interface cable, demo board, power supply and Getting Started tutorial manual.
About Macraigor Systems
Macraigor Systems is a leading supplier of JTAG/BDM connection solutions for on-chip debugging of 32 and 64-bit embedded microprocessors. Macraigor Systems’ solutions are designed for price-sensitive customers. These solutions include a suite of software tools that supports Windows 9x, NT, ME, XP, 2000, Linux and Solaris host systems. Macraigor Systems supports all major embedded microprocessor architectures, including AMD, ARM, CPU32 Series, PowerPC, MIPS and the XScale microarchitecture.
Macraigor Systems LLC, OCDemon and J-SCAN are trademarks or registered trademarks of Macraigor Systems LLC in the U.S. and/or internationally.
North American Sales Contact: Macraigor Systems LLC, PO Box 471008, Brookline Village, MA 02447-1008, Tel: 617-739-8693; Fax: 617-739-8694.