Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, introduced Cadence(R) Precision Router, a space-based, full-chip and block routing solution for advanced mixed-signal, analog and custom digital designs. The product speeds design and manufacturing convergence by allowing designers to model manufacturing effects during the design process for design performance closure and faster time-to-volume manufacturing ramp-up.
Complex interconnect rules, including those at 65 and 45 nanometers, challenge the physical modeling capability of traditional shape-based and gridded routers. Cadence Precision Router uses a three-dimensional, space-based modeling approach to analyze true shapes and intervening physical spaces to handle the complexity inherent in ever-increasing design sizes and shrinking process geometries. This model provides greater accuracy, precision and flexibility than shape-based approaches in creating, checking and manipulating interconnects, and minimizes the steps to design and manufacturing convergence.
Cadence Precision Router operates seamlessly with the Virtuoso(R) custom design platform and provides a hierarchical and constraint-driven design closure environment with highly incremental interactive and automatic routing. Cadence Precision Router was architected to optimize tiered and preferred manufacturing rules concurrently with electrical objectives, allowing designers to achieve higher quality results in the shortest amount of time. Silicon-validated results for Cadence Precision Router have shown orders of magnitude improvement in performance and capacity. The product also features multi-threaded routing for fast turnaround on the large designs that are common at leading-edge process nodes.
“Cadence Precision Router reduced our time-to-closure, compared to our previous design methodology,” said Mark Papermaster, vice president of Microprocessor and Systems Technology Development at IBM Corp. “By leveraging the solution’s tiered constraint system, we were able to address our sophisticated manufacturing and high-performance design constraints with excellent quality of results. As an early partner for Cadence’s next-generation, space-based, interconnect system, we saw the value of a single platform for design-for-manufacturing (DFM) and design-for-yield (DFY) interconnect optimization and creation. As a result, we have adopted both Cadence Chip Optimizer and Cadence Precision Router for our 65- and 45-nanometer microprocessor designs.”
With shrinking process geometries, designers must address constantly evolving design rules, satisfy electrical performance targets, manage ever-increasing design sizes and even perform time-consuming, manual intervention after routing. To meet these challenges, Cadence Precision Router offers a gridless, three-dimensional, space-based routing architecture. This solution overcomes the performance and capacity limitations of shape-based routers, and the accuracy and flexibility limitations of gridded routers, allowing designers to model advanced manufacturing processes and design constraints that are used up front in the design process for maximum control and exceptional results. Especially suitable for high-performance blocks and full-chip designs, Cadence Precision Router also features specialty mixed-signal routing, incremental in-core electrical analysis, and DFM and DFY optimization.
“The deep level of collaboration between Cadence and IBM has produced great results in improving turnaround time and yield optimization,” said Leon Stok, director of EDA at IBM Corp. “Cadence Chip Optimizer and Cadence Precision Router provide an outstanding, modular platform for tight integration with our internal toolset. The cooperation between Cadence and IBM is an excellent example of the collaboration needed to create next-generation, electrically- and manufacturing-aware physical implementation solutions.”
Cadence Precision Router, along with Cadence Chip Optimizer, is built on innovative technology developed in Cadence’s Project Catena technology incubator and can be applied to a broad range of design styles and process nodes. Using Cadence Precision Router in their design flows, leading integrated device manufacturers worldwide have produced tapeouts through 45 nanometers in the consumer, business and computing markets.
“Process variability, increasingly complex design rules and manufacturing effects from lithography and chemical mechanical polishing (CMP) are becoming first-order effects,” said Ted Vucurevich, CTO of Advanced Research and Development at Cadence. “To tackle these issues, we’ve developed an entirely new architectural approach for Cadence Precision Router where physical, electrical, and logical perspectives can be presented to the designer all at once. This approach is the cornerstone of convergence and paves the way for designers to achieve the superior quality of results, high capacity and increased throughput needed for routing tomorrow’s most advanced designs.”
Cadence Precision Router is part of Cadence’s growing family of design and manufacturing closure technologies that help designers address both design performance and manufacturing and yield issues throughout the design flow. Cadence Precision Router is an OpenAccess-based application that works seamlessly with the Virtuoso custom design platform and is complementary to the Encounter(R) digital IC design platform.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.