Lattice Rolls Out IP Cores for LatticeSC Extreme Performance FPGA

Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of an extensive intellectual property (IP) portfolio for the LatticeSCTM Extreme PerformanceTM FPGA family. The portfolio includes forty-four IP cores, including both Lattice-created ispLeverCORETM blocks and third-party ispLeverCORE Connection blocks. These new IP cores are in addition to the pre-engineered MACOTM (Masked Array for Cost Optimization) IP blocks available on LatticeSCM FPGAs. Lattice also has made most of its initial ispLeverCORE blocks for the LatticeSC family available with its new IPexpressTM flow, enabling easy user-controllable configuration of many popular IP cores.

Since the introduction of the LatticeSC device family in February 2006, Lattice has delivered IP cores for customers who need system solutions and faster time-to-market for communications, connectivity, controllers and DSP applications. The Lattice ispLeverCORE IP portfolio comprises a range of in-demand technologies including PCI, CPRI, OBSAI, Ethernet, DDR2 and encoders/decoders. Lattice ispLeverCORE Connection partners CAST, DCD, Elliptic and Northwest Logic have made additional and significant contributions to the portfolio.

“We’ve already delivered the highest performance and most robust feature set in the industry for high-end FPGAs. Now we and our partners have delivered comprehensive IP support for popular standards, fast integration and high performance in less than four months, which is unprecedented,” said Stan Kopec, Lattice corporate vice president of marketing. “Customers designing with LatticeSC devices can quickly and easily incorporate our ispLeverCORE and ispLeverCORE Connection IP blocks with our IPexpress flow and our ispLEVER(R) software design tool suite, enabling fast system solutions and accelerated time-to-market.”

LatticeSC PURESPEED I/O and Physical Coding Sublayer Enhance IP Performance
The LatticeSC device family includes several pre-fabricated and optimized I/O and physical layer circuits to simplify implementation and enhance performance for the most demanding designs. In particular, the DDR and DDR2 SDRAM controller IP cores work with gearing circuitry on both input and output register blocks residing within the LatticeSC’s PURESPEEDTM I/O interface in order to ensure timing synchronization of data buses at the interface. Dedicated data alignment and DQS circuitry is also included in the PURESPEED I/O interface for DDR and DDR2. The 10 Gb Ethernet MAC IP core also benefits from embedded hard logic in the exclusive LatticeSC Physical Coding Sublayer (PCS), including clock tolerance compensation, channel alignment, 8b/10b encoding and word alignment/link synchronization.

Portfolio of ispLeverCORE IP Blocks Offered by Lattice and Partners
The Lattice ispLeverCORE blocks supported by the IPexpress design flow include several versions of conventional PCI including PCI Master/Target 64-bit/66 MHz, Block Viterbi Decoder, DDR 200 SDRAM Controller, DDR2 200 SDRAM Controller, Soft Error Detection, CPRI, OBSAI and 10 Gb Ethernet MAC. The 10/100/1000 Ethernet MAC and DMA Controller also are available with the standard ispLEVER design flow.

Lattice’s ispLeverCORE Connection partners CAST, DCD, Elliptic and Northwest Logic provide the following cores:

  • CAST
    C1394A, USB 1.1, USB 2.0, USB 2.0 OTG, SPI Master/Slave, 16550 UART, SDLC, C8051, R8051
  • DCD
    I2C Master/Slave, I2C Master, I2C Slave, I2C Slave-Base, SPI Master/Slave with FIFO, SPI Master/Slave, SPI Slave, 16450 UART, 16550 UART, 16750 UART, DP8051, DP8051 CPU
  • Elliptic
    DES/3DES, AES, Tiny AES
  • Northwest Logic
    PCI Express x1, PCI Express x4, PCI Express x8

About LatticeSC Extreme Performance FPGAs
Announced in February 2006, LatticeSC Extreme Performance FPGAs deliver the highest performance and most robust feature set of any programmable logic product in the industry. The LatticeSC FPGA combines up to thirty-two 3.8 Gbps SERDES channels with an innovative Physical Coding Sublayer (PCS) to provide a breadth of support for interface protocols including PCI Express, Serial RapidIO, Ethernet, Fiber Channel, XAUI and SONET/SDH. Source synchronous I/O standards such as RapidIO, HyperTransport, SPI4.2, SFI-4, UTOPIA, XGMII and CSIX, and memory standards including SDR, DDR1, DDR2, QDR2 and RLDRAM are implemented with dedicated PURESPEED I/O logic that delivers up to 2 Gbps parallel I/O performance. The LatticeSC device also includes exclusive MACO (Masked Array for Cost Optimization) pre-engineered IP in structured ASIC blocks for low cost and low power system-level integration.

The LFSC25 in the 900fpBGA package is the first LatticeSC device available and is currently sampling. Projected pricing for the basic LFSC25 in the 900fpBGA package in quantities of 25,000 for shipment in 2007 is $49.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPACâ) and Programmable Digital Interconnect Devices (ispGDXâ). Lattice also offers industry leading SERDES products.

Lattice continues to deliver “More of the Best” to its customers with comprehensive solutions for system design, including an unequaled portfolio of high performance, non-volatile and low cost FPGAs.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), LatticeSC, Extreme Performance, IPexpress, ispLEVER, ispLeverCORE, ispPAC, ispGDX, MACO, PURESPEED and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.