Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced today the industry’s first automated end-to-end transaction-based flow from architectural modeling to full system validation. In contrast to the typical disjointed system verification process where models for system-level simulation are different from the models for acceleration/emulation, the newly enhanced Incisive(R) Enterprise solution combines verification management technology, SystemC/mixed-language simulation, and hardware acceleration/emulation for customers verifying and validating complex systems on chip (SoC) and systems. By adopting the new Incisive Enterprise solution customers can increase overall productivity, predictability, and system-level quality.
Engineers can now easily describe and track transaction-level tests and system-level assertions in a master verification plan (vPlan), control system-level regression tests on high-performance software and hardware engines, analyze failures, rank tests against coverage targets, and aggregate total system coverage. The Cadence solution also includes a new SimVision debug environment. The enhanced SimVision includes a common single design hierarchy, source viewer, unified multi-language assertion browser and waveform debugger – all with multiple abstraction levels and engines for system-level debug and analysis. The Incisive Plan-to-Closure methodology has been updated to include transaction-based acceleration (TBA) and transaction-level modeling (TLM) methodologies to guide design and verification teams through the verification process.
“System-level verification of complex SoC designs is an important piece of the overall ESL market and typically includes forms of SystemC TLM, TBA and emulation. Cadence is a major contributor and key player driving the TLM, SystemC and SCE-MI standards,” said Brian Bailey, chairman of the Accellera Interfaces committee. “This latest announcement from Cadence promises to add new productivity capabilities and methodology extensions addressing the migration from simulation to acceleration with full consistency between them. In addition, new capabilities can be expected for managing and tracking system-level verification progress and Verification IP re-use.”
New system-level capabilities have been added to the executable vPlan to work with Incisive Enterprise Manager. For example, Enterprise Manager now tracks coverage for directed tests and assertions for software and hardware-based verification engines – based on a common, executable vPlan. Enhanced transaction-based acceleration capabilities include new verification IP and an exciting new hybrid mode that combines transaction-based acceleration with in-circuit emulation. This capability supports multiple sources of stimuli that originate from software testbenches and from the physical target systems. It also enables design, verification and entire validation teams to migrate their verification process smoothly from simulation to silicon.
“Cadence’s transaction-based system verification solution allowed us to use a mixed RTL/SystemC environment connecting high-level models, verification components, RTL and netlist components from multiple vendors. We are extremely pleased with the seamless integration of Verilog and SystemC components,” said John Mucci, president of SiCortex, Inc. “Cadence is effectively addressing our system-level verification challenges.”
The system-level solution includes new Verification Intellectual Property (VIP) supported throughout the Incisive platform. The VIP improves system verification productivity by providing off-the-shelf system verification environments. For the first time, customers can now reuse the same transaction-based and assertion-based VIP in a simulator and accelerator without having to change their design or testbench code — and get congruent results. The new transaction-based VIP support ARM(R) AMBA(R) 2 AHB and AMBA 3 AXI(TM) protocols, PCI Express, and Gigabit Ethernet protocols. The new assertion-based VIP support ARM AMBA 2 AHB and AMBA 3 AXI protocols, USB, and Gigabit Ethernet protocols. Two SpeedBridge emulation rate adapters, SAS and SATA, have been added to the existing SpeedBridge library. The rich SpeedBridge offerings target high-demand areas such as storage area networks, wireless and personal entertainment applications and are supported by both the Xtreme and Palladium series.
“Based on recent surveys and analyst data, Cadence is clearly leading the market in system-level verification,” said Ran Avinun, group director, System Level Verification marketing for Cadence. “Our new enhanced transaction-based system verification solution increases design verification productivity and ensures the most predictable path to system-level quality.”
Cadence’s new transaction-based system verification solution is available now.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Cadence, the Cadence logo and Incisive are registered trademarks of Cadence Design Systems, Inc.