Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence(R) device and interconnect models, design flows and design for manufacturing (DFM) technologies support Taiwan Semiconductor Manufacturing Company’s (TSMC) 65-nanometer technology. By providing designers an integrated methodology to address 65 nanometers, Cadence can help shorten the design cycle, maximize first-pass silicon success, and address manufacturing issues throughout the design chain.
“Lowering barriers for advanced design is critical to increasing the adoption rate for 65-nanometer technology,” said Edward Wan, senior director of Design Services marketing at TSMC. “We work with Cadence to achieve a faster ramp to volume by allowing designers to address manufacturing and lithography effects.”
Technology files for Cadence QRC Extraction, as well as device models for the Cadence Virtuoso(R) Spectre(R) Circuit Simulator, are now available from TSMC. These technology files and device models have been validated for TSMC’s 65-nanometer Nexsys process design rules. Designers using Virtuoso UltraSim Full-chip Simulator and Virtuoso AMS Designer Simulator can use the same device models as Virtuoso Spectre Circuit Simulator via the Common Model Interface. Cadence QRC Extraction accounts for process variation effects to ensure design manufacturability. Cadence simulation technology has also been updated with the latest BSIM device models incorporating key 65-nanometer effects on device characteristics, such as LOD/STI and well proximity, to enhance silicon-accurate results for designs using TSMC’s 65-nanometer Nexsys(SM) process.
65-nanometer designs face complex issues, such as an exponential increase in leakage power, tight manufacturing parameters, and new extraction requirements. Cadence and TSMC are continuing their design-chain collaboration to address these issues through comprehensive design kits and reference flows for TSMC’s 65-nanometer process. These design kits and flows help provide a smooth path from design through physical implementation for customers using the Cadence Encounter(R) digital IC design, Virtuoso(R) custom design, and Allegro(R) system interconnect design platforms.
Cadence DFM technologies that are tied to TSMC’s 65-nanometer process include critical area analysis (CAA), lithography process checking (LPC), and the physics-based modeling of chemical mechanical polishing (CMP) effects required for analysis of full-chip thickness variation. TSMC process-specific manufacturing data is incorporated into these technologies to improve design capabilities and productivity for designers working on complex 65-nanometer SoCs.
The Cadence DFM approach addresses nanometer defect yield issues with the Cadence SoC Encounter(TM) GXL RTL-to-GDSII system, which provides CAA and optimization within the Encounter platform. This enables yield optimization to be considered concurrently with power, timing, signal integrity and area at any point in the design flow – from prototyping and physical synthesis to manufacturing-aware extraction and chip finishing. For LPC, Cadence provides resolution enhancement techniques (RET) capabilities within the design environment to identify locations in the design where common lithography process variations may cause severe printability issues that would affect yield. In addition, Cadence technology for CMP modeling of full-chip thickness variation accurately predicts systematic variation in interconnect layer thickness that results from planarization operations (i.e., CMP). The resulting predictions can be used to identify thickness-related yield hot spots or to shrink overly conservative thickness guardbands.
“Cadence continues to take a leadership role in accelerating time to volume for 65-nanometer designs,” said James Miller, Jr., executive vice president, Products and Technologies Organization, at Cadence. “At advanced process nodes, designers face increasing impact from physical and lithographic effects that significantly degrade circuit performance and yield. By providing solutions that more accurately model 65-nanometer manufacturing effects, we can help designers anticipate manufacturing and lithography-based concerns during the design process, enabling more manufacturable, high-yielding products to be brought to market sooner.”
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry.
Cadence, the Cadence logo, Allegro, Encounter, Spectre, and Virtuoso are registered trademarks, and SoC Encounter is a trademark, of Cadence Design Systems, Inc.